From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752184AbcDYWO1 (ORCPT ); Mon, 25 Apr 2016 18:14:27 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:62836 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751829AbcDYWO0 (ORCPT ); Mon, 25 Apr 2016 18:14:26 -0400 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: Masahiro Yamada , Russell King , linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs Date: Tue, 26 Apr 2016 00:13:53 +0200 Message-ID: <51817650.ZWFPAKxQiK@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <1460703947-12539-1-git-send-email-yamada.masahiro@socionext.com> References: <1460703947-12539-1-git-send-email-yamada.masahiro@socionext.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:OFzFkj6m6F3qRV+JePsx5hzSYxS4NpbdKb9EhLJOXRZ1iY6QwaZ pL+GBermENq+EETSN6w9ySUqp2MpzNpuQkhFA6gzJ6mf333V/X4Nco3KYL2pK9aTPyUzgDD lWBVGTXGWAX1tn4GrQEqEmKcVYYzz5+j/G07kV2Xumwj321mhQTMcnmcD7eq1iTjwi+2/k9 zDLcICya8uhRWZfmiKsZA== X-UI-Out-Filterresults: notjunk:1;V01:K0:X6nnTFFzc4o=:Bp7dQU7jfiwTfmSBG+Sur0 +TdaOUzG/5XjdeKp/Bb6lO60Y0uDXNXaIjghiDaFlEf4PJgHLVO21ncCwazuEfShM/HOjqFzR bm0dhKiDm2q4nwRlAFNmu90HfYjoW3fv54iCqJkMeING/Jmx1BjZFLimR9rWuKb/sVHw7L9dw 0rXQu3+MzbpLV6IDbKyA7lXzn8tCSN8ChQ0jSeTk1PaEVYjOqsugSZzkEXcvdtiS9Pr7v8Sg5 d6f7xmYRMF89lFzOo0Cg9HK/3X9IRV4+m6lWwHCIHAHSqEqZLFLQBjbDQgP4wNsmwA73HaDnP ak8sSRi2q/JlenTJrd7mCH1ufn1r21HBYwTyrnAC7LutP6fPkER7BtkCqPXkXD8oQlWHrf16u wpDfYObg84FDtXJCLo9f/ZM15MKMsXK1P9RDsHLrkldALacu+EnUG8yk1qnEZwRxGyKUBR2ix Y2ViBzQhd4SngvthmygF44BVDQqWc2pqjXZQZGb9uQ0wFGR4nLVwMe8nbw5DK9dCFi7bjk7qh Ol9v3T7TE+FsDGok2rCoU98ImboqK44qNauuvWvuG9DzxK1ii0sBO7hgqTUTINW7Um+O8GYxY floSVPCcle/9hXCzA60iyqH59LiS6na/16a+U2wg9rQwdcaGcTaRSUJ4ItGMgZ+JUZQnTFA5U 2P7zO3AjkznSpSi8clcHQGVWuG8VXpq413yCEzCLAa8DzDyxpP1c1SAzro1ZM+W9lwzJRy8Z8 E3+WzmCFMoFkoED8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: > This outer cache allows to control active ways independently for > each CPU, but currently nothing is done for secondary CPUs. In > other words, all the ways are locked for secondary CPUs by default. > This commit fixes it to fully bring out the performance of this > outer cache. > > There would be two possible ways to achieve this: > > [1] Each CPU initializes active ways for itself. This can be done > via the SSCLPDAWCR register. This is a banked register, so each > CPU sees a different instance of the register. > > [2] The master CPU initializes active ways for all the CPUs. This > is available via SSCDAWCARMR(N) registers. They are mapped at > the address SSCDAWCARMR + 4 * N, where N is the CPU number. > > Currently, the outer cache frame work does not support a per-CPU > init callback. So this commit adopts [2]; the master CPU iterates > over possible CPUs setting up SSCDAWCARMR(N) registers. > > Unfortunately, the register offsets of SSCDAWCARMR(N) are different > by SoC. We can live with it by checking the version register. > > Signed-off-by: Masahiro Yamada > Applied to next/soc, thanks! I'm a little lost with the patches you send, could you check that I have applied all the ones you sent for 4.7 so far? Arnd