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Wed, 18 Dec 2019 19:46:02 +0000 From: Tom Lendacky To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Brijesh Singh Subject: [PATCH v1 2/2] KVM: SVM: Implement reserved bit callback to set MMIO SPTE mask Date: Wed, 18 Dec 2019 13:45:47 -0600 Message-Id: <519cd0f0f2ff7fa0e097967546506c07e2e56dda.1576698347.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Content-Type: text/plain X-ClientProxiedBy: DM6PR21CA0007.namprd21.prod.outlook.com (2603:10b6:5:174::17) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 620533ef-a3a2-4acb-e519-08d783f2e996 X-MS-TrafficTypeDiagnostic: DM6PR12MB2876:|DM6PR12MB2876: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; 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If disabled, then the physical address width is not reduced, so bit 51 can be used, unless the physical address width is 52. In this case, return zero for the mask. Fixes: 28a1f3ac1d0c ("kvm: x86: Set highest physical address bits in non-present/reserved SPTEs") Signed-off-by: Tom Lendacky --- arch/x86/kvm/svm.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 122d4ce3b1ab..a769aab45841 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -7242,6 +7242,46 @@ static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu) (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT)); } +static u64 svm_get_reserved_mask(void) +{ + u64 mask, msr; + + /* The default mask, used when memory encryption is not enabled */ + mask = 1ull << 51; + + /* No support for memory encryption, use the default */ + if (cpuid_eax(0x80000000) < 0x8000001f) + return mask; + + /* + * Check for memory encryption support. If memory encryption support + * is enabled: + * The physical addressing width is reduced. The first bit above the + * new physical addressing limit will always be reserved. + */ + rdmsrl(MSR_K8_SYSCFG, msr); + if (msr & MSR_K8_SYSCFG_MEM_ENCRYPT) { + /* + * x86_phys_bits has been adjusted as part of the memory + * encryption support. + */ + mask = 1ull << boot_cpu_data.x86_phys_bits; + + return mask; + } + + /* + * If memory encryption support is disabled: + * The physical addressing width is not reduced, so the default mask + * will always be reserved unless the physical addressing width is 52, + * in which case there are no reserved bits, so return an empty mask. + */ + if (IS_ENABLED(CONFIG_X86_64) && boot_cpu_data.x86_phys_bits == 52) + mask = 0; + + return mask; +} + static struct kvm_x86_ops svm_x86_ops __ro_after_init = { .cpu_has_kvm_support = has_svm, .disabled_by_bios = is_disabled, @@ -7379,6 +7419,8 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = { .need_emulation_on_page_fault = svm_need_emulation_on_page_fault, .apic_init_signal_blocked = svm_apic_init_signal_blocked, + + .get_reserved_mask = svm_get_reserved_mask, }; static int __init svm_init(void) -- 2.17.1