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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d022c4090fsm11131425ad.80.2026.07.29.06.18.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jul 2026 06:18:11 -0700 (PDT) Message-ID: <5215ceda-0f13-44ce-93ef-41985979ce7f@oss.qualcomm.com> Date: Wed, 29 Jul 2026 21:18:05 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> <20260724-qcom_ipq5210_cmnpll-v1-9-a8b8679d215f@oss.qualcomm.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: KolZfRTq_8eGWtY1MmeGDeqvcu7_n3Lh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI5MDExMCBTYWx0ZWRfXwpbSfdUeclSs /g9fKG2syrnyYKg+YUv2v/i7/utx4IYamGyP8ta+7LbhqMrttKKtgJcQA33E0jpHSDwUteEKanh NPlMTFulrsvDjd7PI+cGT/r3uduC8McDJK/qPDBF1OIbXkAOERskLWVqC3i3RE+MklFZkCjdLwk iXylwmiurHfEP6RuQkDK8hEs5WhBSiM76mI7uXyP9hnbxVdFPJp5zWpIaW2QlRJxVBqM1l6RKy/ bjBD9ntBeUVJZCR/41UGahEULtvsYAmAg8VIHQUnknh2+9HgyoJJJBwe4nF6Z2WDw+hWi/C72D4 jd+HwglRDDya4dfU4uWU2MBuq0Usa4bFJOB8C1xhexXzOuOiFnr8FAWFxjL3pbljqqHG0xUDpF1 z/NIwGlOGCEaKWKAll5TGrkBMxayhKd+Ql7EM93Ttgh+n3CGthZ6g94omUr1eHFpmmxfZAHaNAB VAZkzwb21a47/WPKAqg== X-Proofpoint-ORIG-GUID: KolZfRTq_8eGWtY1MmeGDeqvcu7_n3Lh X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI5MDExMCBTYWx0ZWRfX44AN5CopQSZO N12XI6FpQRlU0MFejvNSCUzgtnpI1o58EsTOrhaua3n41eQsg7I5/LyB8CgGKzf5oDPO4UyQlS1 AUh+1w9K9o+c0TlnyDxACM42SQcaWXQ= X-Authority-Analysis: v=2.4 cv=VZHH+lp9 c=1 sm=1 tr=0 ts=6a69fd94 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=4OnM024n7VW8eM1T7MUA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-29_05,2026-07-28_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607290110 On 7/28/2026 5:32 PM, Konrad Dybcio wrote: > On 7/24/26 5:00 PM, Luo Jie wrote: >> Some CMN PLL output clocks require a hardware gate in addition to a >> fixed rate. The gate control bits reside in the register >> CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered as a >> composite clock combining a clk_fixed_rate provider with a clk_gate. > > Would toggling this register in .enable/.disable not be good enough? > Do we need to register a separate gate? > > Konrad Yes. Toggling the bit directly in custom .enable/.disable is simpler and more consistent with the rest of this driver (every other clock here uses regmap). Will switch to a single clk_hw with hand-written .enable/.disable/.is_enabled/.recalc_rate ops on CMN_PLL_OUTPUT_RELATED_1.