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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434accae18sm13133819b3a.17.2026.06.16.02.44.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jun 2026 02:44:39 -0700 (PDT) Message-ID: <521918c4-fea2-4fc3-bfc6-ab2abc275ec0@oss.qualcomm.com> Date: Tue, 16 Jun 2026 17:44:34 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 29/39] drm/msm/dp: add an API to initialize MST on sink side To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-29-b20518dea8de@oss.qualcomm.com> <32jtwnkusxultvsgvnalrvccfkcyk7744yf4d42pqm7wudysvt@l4pnrzfxh2f4> <1fe8d286-7182-49ed-b6fc-dfa3766f851a@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE2MDA5OCBTYWx0ZWRfX0mfAWQqD+rH+ I1oRYm5FOGOiAbWsoYIRiXieyNBpn79bN4MVuPA060kXJezwq7VBAGKPCKfgADptRdAiE8nhJjo fTuy9sG3oQfkvaEkq9DCEF02M692fLIP4auMKud2XCICDdfPDHubY5+Q/YJ5nLh6gTSC/6zI1BC 9rsimYvNLL4jqi2F2G9Rx/5JobyHf8GLubGQMgs3LwChUPpXvtM+e4u6eEWW+oz4QYH+miNJ1fd dCIGLYvlnGIKsKrGyOnKOI6UH7Epi6EiRxGUyNSF7p02iIiqqvfFx+oGTA4Ji414ehEL0RAsoSr ZsTgBEX1yH/9sqnadHFFPC2pss2QxkSugDRMeK9MlRi1Oe4xI/+qdwlHugxo0q0+sA2iP2Wv/DR heBm+t5GHFlBAuXkdRgFoY2SDQHKyIqAERG3LFMQDnRKxAwH1zaI4X3bYF6Jb9HWaTk348HfBJ+ 7PpBFudiT1aHYKOFyqQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE2MDA5OCBTYWx0ZWRfXzYuL0uB53/zE s/H/3MI3ZkXHN8Mzao77piB5uryaZIec4WNKHKesNtLxKoq/gCndxSZuLo4Zo/Epo/5gKMYWfFl wusj2uKUIMmDmdJ9+ca0Vd2W9drAGVI= X-Proofpoint-ORIG-GUID: l42ZA3naXVPV71xokd3RGQ2wyYUARh9s X-Authority-Analysis: v=2.4 cv=dZawG3Xe c=1 sm=1 tr=0 ts=6a311b09 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=iQs2M_KxR2iUDnadKT8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: l42ZA3naXVPV71xokd3RGQ2wyYUARh9s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-16_02,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606160098 On 6/16/2026 8:45 AM, Dmitry Baryshkov wrote: > On Mon, Jun 15, 2026 at 05:02:27PM +0800, Yongxing Mou wrote: >> >> >> On 4/12/2026 8:15 AM, Dmitry Baryshkov wrote: >>> On Fri, Apr 10, 2026 at 05:34:04PM +0800, Yongxing Mou wrote: >>>> From: Abhinav Kumar >>>> >>>> If the DP controller is capable of supporting multiple streams >>>> then initialize the DP sink in MST mode by programming the DP_MSTM_CTRL >>>> DPCD register to enable MST mode. >>>> >>>> Signed-off-by: Abhinav Kumar >>>> Signed-off-by: Yongxing Mou >>>> --- >>>> drivers/gpu/drm/msm/dp/dp_display.c | 57 ++++++++++++++++++++++++++++++++----- >>>> 1 file changed, 50 insertions(+), 7 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c >>>> index 8ae690ce2b9f..abf26951819a 100644 >>>> --- a/drivers/gpu/drm/msm/dp/dp_display.c >>>> +++ b/drivers/gpu/drm/msm/dp/dp_display.c >>>> @@ -14,6 +14,7 @@ >>>> #include >>>> #include >>>> #include >>>> +#include >>>> #include >>>> #include "msm_drv.h" >>>> @@ -270,6 +271,40 @@ static int msm_dp_display_lttpr_init(struct msm_dp_display_private *dp, u8 *dpcd >>>> return lttpr_count; >>>> } >>>> +static void msm_dp_display_mst_init(struct msm_dp_display_private *dp) >>>> +{ >>>> + const unsigned long clear_mstm_ctrl_timeout_us = 100000; >>>> + u8 old_mstm_ctrl; >>>> + struct msm_dp *msm_dp = &dp->msm_dp_display; >>>> + int ret; >>>> + >>>> + /* clear sink MST state */ >>>> + drm_dp_dpcd_read_byte(dp->aux, DP_MSTM_CTRL, &old_mstm_ctrl); >>>> + >>>> + ret = drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, 0); >>>> + if (ret < 0) { >>>> + DRM_ERROR("failed to clear DP_MSTM_CTRL, ret=%d\n", ret); >>>> + return; >>>> + } >>>> + >>>> + /* add extra delay if MST old state is on*/ >>>> + if (old_mstm_ctrl) { >>>> + drm_dbg_dp(dp->drm_dev, "wait %luus to set DP_MSTM_CTRL set 0\n", >>>> + clear_mstm_ctrl_timeout_us); >>>> + usleep_range(clear_mstm_ctrl_timeout_us, >>>> + clear_mstm_ctrl_timeout_us + 1000); >>> >>> For 100 ms you should be using msleep() instead. But where is that >>> timeout coming from? >>> >> Will switch to msleep(100). >> >> The 100 ms is an empirical workaround carried over from downstream — some >> sinks don't exit MST immediately after writing DP_MSTM_CTRL = 0, and >> re-enabling MST too quickly broke topology probe. > > Comment. > Got it. >> It's not a DP spec >> requirement, and other drivers (drm_dp_mst core, i915, amdgpu, nouveau) >> don't have an equivalent delay. > > Why? > This comes from the downstream implementation and was added due to issues observed with some dongles, which reportedly required a ~100 ms delay. However, it’s unclear whether such a long delay is actually necessary (e.g. if a shorter delay would be sufficient). Alternatively, we could follow nouveau and avoid adding the delay for now, and only introduce it if it turns out to be required. >> >>>> + } >>>> + >>>> + ret = drm_dp_dpcd_write_byte(dp->aux, DP_MSTM_CTRL, >>>> + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); >>> >>> Isn't it too early to enable MST? (I don't remember this part of the >>> standard). >>> >> No, this follows the DP 1.4a MST spec. DP_MSTM_CTRL must be set before >> topology discovery. Topology discovery uses AUX sideband messages, which >> don’t require link training. >> So we enable MST first, then discover topology, and only do link training >> and payload allocation later in atomic_enable(). > > Ack, thanks. > >