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Tue, 28 Apr 2026 00:04:24 -0700 (PDT) X-Received: by 2002:a17:90b:1dd1:b0:35f:b46e:e329 with SMTP id 98e67ed59e1d1-36491f8a604mr2022941a91.6.1777359863611; Tue, 28 Apr 2026 00:04:23 -0700 (PDT) Received: from [10.92.193.222] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36490fd57dasm1670321a91.17.2026.04.28.00.04.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Apr 2026 00:04:23 -0700 (PDT) Message-ID: <5233eb62-7b6c-45c6-b24c-af4db5248352@oss.qualcomm.com> Date: Tue, 28 Apr 2026 12:34:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/3] PCI: qcom: Program T_POWER_ON To: Manivannan Sadhasivam Cc: Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com> <20260404-t_power_on_fux-v4-3-2891391177f4@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: RheZxF1-n_6AwGfhmhMMGNIQe6OPzaDU X-Authority-Analysis: v=2.4 cv=PcrPQChd c=1 sm=1 tr=0 ts=69f05bf8 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=TGbq2H1_L8zW2zdi06cA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: RheZxF1-n_6AwGfhmhMMGNIQe6OPzaDU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI4MDA2MyBTYWx0ZWRfX/Pb2a2WqQ2SC kpf96dldN82rlRwPsgW2qGtFJNyndtAPF4wWyo2WVxuFfOtT9UusybIyWLgdrqJ0+yflbQ3qRAn yYCUzoN43r3pLsGLJoP2FylwiCWtqjZYfXmIEWTEwzNtWkj6Ohqjy3a/+LJb8z1ke0E32KxlEZo 8PcXHH41SwcloggjC9i3KyDId42fZi0S8zsz3q2RpkTxPiE8HyTHu1P7W9m200u6A1UTOJLr220 4AC+H2BbkurZlPZabVLXnIVYk1kZb/00Hg63AQz6vvAdKrviWQbdyHXm65J7O3O498v4XlAxO6d NI4AKAP0c+/DLgvPeqkQDBAN7y5xgdhLhJoV8riiQr5jARV8kLN4HcJa8s4348wHD2BJ8SVZgHK 51P9jmj7ltXCtUNlR+CJbZPZQXfWu+McasPBtBPj2WI3RQyio5OmpcHK/rZIk9ETfOAI/1FxJlr 9EiAT0M1w0l7aXgnOhw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_01,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 malwarescore=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280063 On 4/10/2026 10:25 PM, Manivannan Sadhasivam wrote: > On Sat, Apr 04, 2026 at 01:47:20PM +0530, Krishna Chaitanya Chundru wrote: >> Some platforms have incorrect T_POWER_ON value programmed in hardware. >> Generally these will be corrected by bootloaders, but not all targets >> support bootloaders to program correct values due to that >> LTR_L1.2_THRESHOLD value calculated by aspm driver can be wrong, which >> can result in improper L1.2 exit behavior and if AER happens to be >> supported and enabled, the error may be *reported* via AER. >> >> Parse "t-power-on-us" property from each root port node and program them >> as part of host initialization using dw_pcie_program_t_power_on() before >> link training. >> >> This property in added to the dtschema here[1]. >> >> Signed-off-by: Krishna Chaitanya Chundru >> Link[1]: https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundru@oss.qualcomm.com/ >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 67a16af69ddc75fca1b123e70715e692a91a9135..a8f82f860c08fe2eabad2c0eed541b8dd121215e 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -269,6 +269,7 @@ struct qcom_pcie_perst { >> struct qcom_pcie_port { >> struct list_head list; >> struct phy *phy; >> + u32 l1ss_t_power_on; >> struct list_head perst; >> }; >> >> @@ -1283,6 +1284,14 @@ static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) >> return 0; >> } >> >> +static void qcom_pcie_configure_ports(struct qcom_pcie *pcie) >> +{ >> + struct qcom_pcie_port *port; >> + >> + list_for_each_entry(port, &pcie->ports, list) >> + dw_pcie_program_t_power_on(pcie->pci, port->l1ss_t_power_on); > Since this writes to the same register, there is no point in iterating over all > ports. Add a TODO here also and write it only once. we will iterate only once in case of single root port. so we are good here. - Krishna Chaitanya. >> +} >> + >> static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >> { >> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> @@ -1317,6 +1326,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >> dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); >> dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); >> >> + qcom_pcie_configure_ports(pcie); >> + >> qcom_pcie_perst_deassert(pcie); >> >> if (pcie->cfg->ops->config_sid) { >> @@ -1759,6 +1770,9 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node >> if (ret) >> return ret; >> >> + /* TODO: Need to move to dwc once multi root port support is added. */ > s/dwc/DWC core > > s/root port/Root Port > > - Mani >