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AJvYcCUuB9QaotRIICMcJV3hO6IYiytLV8qA87L74Dheus3U+f6nv4DFcfbNhGHSTDPLyoxe70URmkYHjzoP0MYR0tJN0fGgGd/jWZzt/35U X-Gm-Message-State: AOJu0YznU4G5O6L9pi1GakwaEQrKV5JaZ1o9j5UCowKg8Jh/9wq4t6he POFdhF9+R+yC0uueW6wtpAg29JNmDn1ayuoB4x3cmQ8m1qGocMSZn98CG8oqgw4= X-Google-Smtp-Source: AGHT+IEzZdSed4XOrE4rETuECmfdaxcVqf4C7+1LXgTcZDv2J71RTHhX+CpK/z2WbiePkXS0N6SWDw== X-Received: by 2002:adf:eeca:0:b0:34b:147f:df67 with SMTP id a10-20020adfeeca000000b0034b147fdf67mr3840631wrp.53.1714046577733; Thu, 25 Apr 2024 05:02:57 -0700 (PDT) Received: from [10.1.1.109] ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id w20-20020adfe054000000b0034a366f26b0sm18062178wrh.87.2024.04.25.05.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 05:02:57 -0700 (PDT) Message-ID: <52403f522a4f7513c5ee5dae48856988f7141825.camel@linaro.org> Subject: Re: [PATCH v2 06/14] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Peter Griffin , mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, jejb@linux.ibm.com, martin.petersen@oracle.com, James.Bottomley@HansenPartnership.com, ebiggers@kernel.org Cc: linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tudor.ambarus@linaro.org, saravanak@google.com, willmcvicker@google.com Date: Thu, 25 Apr 2024 13:02:55 +0100 In-Reply-To: <20240423205006.1785138-7-peter.griffin@linaro.org> References: <20240423205006.1785138-1-peter.griffin@linaro.org> <20240423205006.1785138-7-peter.griffin@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3-1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2024-04-23 at 21:49 +0100, Peter Griffin wrote: > Enable the ufs controller, ufs phy and ufs regulator in device tree. >=20 > Signed-off-by: Peter Griffin > --- > =C2=A0.../boot/dts/exynos/google/gs101-oriole.dts=C2=A0=C2=A0 | 18 ++++++= ++++ > =C2=A0arch/arm64/boot/dts/exynos/google/gs101.dtsi=C2=A0 | 36 +++++++++++= ++++++++ > =C2=A02 files changed, 54 insertions(+) >=20 [...] > + > + ufs_0: ufs@14700000 { > + compatible =3D "google,gs101-ufs"; > + reg =3D <0x14700000 0x200>, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x14701100 0x200>, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x14780000 0xa000>, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x14600000 0x100>; > + reg-names =3D "hci", "vs_hci", "unipro", "ufsp"; > + interrupts =3D ; > + clocks =3D <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, > + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, > + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, > + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, > + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, > + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; > + clock-names =3D "core_clk", "sclk_unipro_main", "fmp", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "ufs_aclk", "ufs_pclk", "sysreg"; > + freq-table-hz =3D <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; > + pinctrl-names =3D "default"; > + pinctrl-0 =3D <&ufs_rst_n &ufs_refclk_out>; The preferred order is pinctrl-0 before pinctrl-names (similar to clock-nam= es and reg-names). Other than that, Acked-by: Andr=C3=A9 Draszik