From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51E4DC54FCB for ; Fri, 24 Apr 2020 15:39:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3133520700 for ; Fri, 24 Apr 2020 15:39:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=cerno.tech header.i=@cerno.tech header.b="x8B2LxEA"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="pWGWRSth" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729088AbgDXPjp (ORCPT ); Fri, 24 Apr 2020 11:39:45 -0400 Received: from wnew2-smtp.messagingengine.com ([64.147.123.27]:32853 "EHLO wnew2-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728545AbgDXPg1 (ORCPT ); Fri, 24 Apr 2020 11:36:27 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.west.internal (Postfix) with ESMTP id CDD4A145B; Fri, 24 Apr 2020 11:36:25 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Fri, 24 Apr 2020 11:36:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=vdM/4XaeVSUc3 VqHyRlaM8vqrseDJanMHFILNJC9PX0=; b=x8B2LxEAMRZyXWK99Sk1PTBTza0SD 83wuoOqnQFNtnXxKA16H7UMcxEi1kjGqVK4+bVBJgpB+lDlUUhBIUt6liQCn/nJ5 57sb3R9gqk+gStMtkLpXrkM2FOpK8qVKJjHBWii1iprx7KDC7sj8OlpFNx8xsdk5 sf94eICOB1+5uXAr7FXoTnU7wYzt6Mfr42KUTX5kEy9gAD/X2lgWh5zkcFcUJj0P 1J5IEuYx7c6WdINdM3pXMfCpnZNbsmaKUlA3IWSt47Pf+1tH5Tgj03yJEKGgyFks OBHZ/+zgh6Ut5QVTgrvgFG8P36vn4SZMylK25aW94tckwIRB3WW8OmJnw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=vdM/4XaeVSUc3VqHyRlaM8vqrseDJanMHFILNJC9PX0=; b=pWGWRSth oBGfTXWypP+i+f1aeAP9zjRMmhKLym6dndfru4+pEk/p2/Ien6t1AqiSHTZcrmsu c+FvoXC1lNCXHoFYCikUgSILXWdPItve3qjsuISm1jApIXdRhtXipy1/mY+wiVxp l6gHyhAQocUEyY3eW9288pCQ3ogjpcbTB4hQKJ/nn3YAYFvM8rWAOmQFRsETJ8PA LjX1VOaMcqapMMG5NZIJEsMkOE/ajgAE9z6LKgqBVwwcCTwhyrMI1iuVItggUc2y ofasyXXT4Yn7xLqCfVnCGt8Owp/laiO9cDQZBfcVNu+hXg4DfVZrYG/TsErfZ471 490lUB0RQMvetg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduhedrhedugdekiecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepofgrgihimhgv ucftihhprghrugcuoehmrgigihhmvgestggvrhhnohdrthgvtghhqeenucfkphepledtrd ekledrieekrdejieenucevlhhushhtvghrufhiiigvpeefkeenucfrrghrrghmpehmrghi lhhfrhhomhepmhgrgihimhgvsegtvghrnhhordhtvggthh X-ME-Proxy: Received: from localhost (lfbn-tou-1-1502-76.w90-89.abo.wanadoo.fr [90.89.68.76]) by mail.messagingengine.com (Postfix) with ESMTPA id 18C933065D93; Fri, 24 Apr 2020 11:36:25 -0400 (EDT) From: Maxime Ripard To: Nicolas Saenz Julienne , Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tim Gover , Phil Elwell , Maxime Ripard Subject: [PATCH v2 45/91] drm/vc4: crtc: Deal with different number of pixel per clock Date: Fri, 24 Apr 2020 17:34:26 +0200 Message-Id: <52788447bf78006f79bdf365ec152db4c838abe4.1587742492.git-series.maxime@cerno.tech> X-Mailer: git-send-email 2.26.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some of the HDMI pixelvalves in vc5 output two pixels per clock cycle. Let's put the number of pixel output per clock cycle in the CRTC data and update the various calculations to reflect that. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 17 ++++++++++------- drivers/gpu/drm/vc4/vc4_drv.h | 3 +++ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 9718df881fab..be264da1a13f 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -282,6 +282,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; + u8 ppc = vc4_crtc->data->pixels_per_clock; /* Reset the PV fifo. */ CRTC_WRITE(PV_CONTROL, 0); @@ -289,17 +290,16 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) CRTC_WRITE(PV_CONTROL, 0); CRTC_WRITE(PV_HORZA, - VC4_SET_FIELD((mode->htotal - - mode->hsync_end) * pixel_rep, + VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, PV_HORZA_HBP) | - VC4_SET_FIELD((mode->hsync_end - - mode->hsync_start) * pixel_rep, + VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, PV_HORZA_HSYNC)); + CRTC_WRITE(PV_HORZB, - VC4_SET_FIELD((mode->hsync_start - - mode->hdisplay) * pixel_rep, + VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, PV_HORZB_HFP) | - VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); + VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, + PV_HORZB_HACTIVE)); CRTC_WRITE(PV_VERTA, VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, @@ -1040,6 +1040,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { static const struct vc4_crtc_data bcm2835_pv0_data = { .hvs_channel = 0, .debugfs_name = "crtc0_regs", + .pixels_per_clock = 1, .encoder_types = { [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, @@ -1049,6 +1050,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = { static const struct vc4_crtc_data bcm2835_pv1_data = { .hvs_channel = 2, .debugfs_name = "crtc1_regs", + .pixels_per_clock = 1, .encoder_types = { [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, @@ -1058,6 +1060,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = { static const struct vc4_crtc_data bcm2835_pv2_data = { .hvs_channel = 1, .debugfs_name = "crtc2_regs", + .pixels_per_clock = 1, .encoder_types = { [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI, [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 487ad72c284d..cda738dbd6c1 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -453,6 +453,9 @@ struct vc4_crtc_data { /* Which channel of the HVS this pixelvalve sources from. */ int hvs_channel; + /* Number of pixels output per clock period */ + u8 pixels_per_clock; + enum vc4_encoder_type encoder_types[4]; const char *debugfs_name; }; -- git-series 0.9.1