From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBD2635949; Mon, 24 Feb 2025 07:31:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740382279; cv=none; b=YXp81VjfkwdIQqARXyBB62ylYgu9t1eHGdlf1niBw6h67xLE0Luk6Urnbd7NfinsZADjobD2w9Q3xMwbRKY8DA2uQwsoXVowZycVCb+a9wVnZFJXH1WLPoqQFk7UpsJT39aEKsf6P5LHUjtNB5w0L/WKVxhpSMW99P93XJvWfTk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740382279; c=relaxed/simple; bh=6Vux+9H8ClY2pt6ERsaHUcicqiz2Ducfgs2C7k+Rxw8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=SYjTQNgFYRSEjjC4hwtrzD3KovMeyoSIx2OCSIIVIAIyiSpZU9Pr2CAdFdNylx39zlQFqFpuNEHq4ESsO/27GRCweXgKAeo2I1/rmq1+oFYmux58PGb+vzEgJ0ADD51VE1ucshTMF2xVv1/g0EcgKrFZ/0QVQj+AjkJOSkSLqBs= ARC-Authentication-Results:i=1; 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h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=AsMt3S/QCcp4YqmtHt2CLr9mFhZdPLKPfYGWnZWAeyYpW+49DCYSWdOGlFb92fml0 G3nrkrG1TkKZtowCnVP5tvKTC36kgXSLPF799IOwFKWIZzwZ1TqzkVPuPk1kyhlXG4 6cCondFoQuo7uAOT/J8EqHc3cizxlWDCT4tLjCzgkEO/OKtDAqS5ofwl0NGj408DrS Z47FSQAGmgrtgn85yfAPo9VgrnaKzXMF7Qzwimn1FpBANCU8sl5SRfTa3U0Dr/MAra PW6cRW26S5wijW5Q5aRXchpRol6BvRYlT4ZvpEupHdRCw5xq9/Us5x9ctV5cgNtNyk nl0hYnNEW3hrg== Message-ID: <52bf4850-b66c-4692-8827-8995793607c3@zytor.com> Date: Sun, 23 Feb 2025 23:30:21 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/5] x86/cpufeatures: Add the CPU feature bit for MSR immediate form instructions To: Borislav Petkov Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, will@kernel.org, peterz@infradead.org, yury.norov@gmail.com, akpm@linux-foundation.org, acme@kernel.org, namhyung@kernel.org, brgerst@gmail.com, andrew.cooper3@citrix.com, nik.borisov@suse.com References: <20250106070727.3211006-1-xin@zytor.com> <20250106070727.3211006-6-xin@zytor.com> <20250222163001.GUZ7n7iRc88PTMQi9_@fat_crate.local> Content-Language: en-US From: Xin Li Autocrypt: addr=xin@zytor.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2/22/2025 8:30 AM, Borislav Petkov wrote: > On Sun, Jan 05, 2025 at 11:07:27PM -0800, Xin Li (Intel) wrote: >> The immediate form of MSR access instructions are primarily motivated by >> performance, not code size: by having the MSR number in an immediate, it >> is available *much* earlier in the pipeline, which allows the hardware >> much more leeway about how a particular MSR is handled. >> >> Add a new CPU feature word for CPUID.7.1.ECX and then the CPU feature bit >> for MSR immediate form. > > Nope, scattered.c. Oh, neat. >> @@ -476,6 +476,9 @@ >> #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */ >> #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classification */ >> >> +/* Intel-defined CPU features, CPUID level 0x00000007:1 (ECX), word 22 */ >> +#define X86_FEATURE_MSR_IMM (22*32+ 5) /* "msr_imm" MSR immediate form instructions */ > > Also no "msr_imm": Documentation/arch/x86/cpuinfo.rst My bad. > > In any case, this patch doesn't belong in this set. > Right. I tried to show that we don't need to make the following changes due to NCAPINTS increased to 23 if this patch is based on this patch set. But if this feature is added through scattered.c, NCAPINTS is not even changed... Thanks! Xin --- diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index de1ad09fe8d7..051d006cc0c6 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -95,7 +96,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 21, feature_bit) || \ REQUIRED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 22)) + BUILD_BUG_ON_ZERO(NCAPINTS != 23)) #define DISABLED_MASK_BIT_SET(feature_bit) \ ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ @@ -121,7 +122,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 21, feature_bit) || \ DISABLED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 22)) + BUILD_BUG_ON_ZERO(NCAPINTS != 23)) #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index c492bdc97b05..c6a1f962185c 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -156,6 +156,6 @@ #define DISABLED_MASK19 (DISABLE_SEV_SNP) #define DISABLED_MASK20 0 #define DISABLED_MASK21 0 -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22) +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 23) #endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h index e9187ddd3d1f..a346db1d078c 100644 --- a/arch/x86/include/asm/required-features.h +++ b/arch/x86/include/asm/required-features.h @@ -100,6 +100,6 @@ #define REQUIRED_MASK19 0 #define REQUIRED_MASK20 0 #define REQUIRED_MASK21 0 -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22) +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 23) #endif /* _ASM_X86_REQUIRED_FEATURES_H */