From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2847F17A922 for ; Wed, 26 Jun 2024 10:52:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719399145; cv=none; b=kYcLtTCx3xm0K/LBvctxOWuBEuZoxS1x7ADv5FSnoXA7Lil3yq4tliURYLRGx7yTblCCEflVR2cfGOaDtqgI5iey1aBAfPUtydWRdLV9IaJyDRWmYtIFwjR6DNH7S6lfqTbXVEjKydJoSpt5D1mrh3BZN7Ad3Qz4Njr0WW//qQQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719399145; c=relaxed/simple; bh=XKE4+a/drYSMQk6Mjnwv3FXxUZAUhdgh/aF+cJdKpsM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=CLu+G5MTFPSUUIIDttCpKlN1QBA36UeXNKXNb7X4eaj+Myuvz3t8iVhznSkqluQgVDYSxOcOgvXmLIBoZTiktz+OYwcDP3/CKSAnhO7OuZAIiI3rGRUeW4FfRXPh00DkB3194MUM+VWtIJ1U8ONQvOUUJpcO1GpLVgNnRnjUotI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=oHkDPAqP; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="oHkDPAqP" Received: from [192.168.88.20] (91-158-144-210.elisa-laajakaista.fi [91.158.144.210]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 83F424CF; Wed, 26 Jun 2024 12:51:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1719399118; bh=XKE4+a/drYSMQk6Mjnwv3FXxUZAUhdgh/aF+cJdKpsM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=oHkDPAqP2yDAOiCYfCuX64Ev8wXb81U5lDLyYcCilaG1LQ6BbTs/ELZWDFSURhNgZ vxAM1Q6Gmfr0ypt3TyICwUb8hAvj0uORQBIyM34eD4PHfhIAMu6jM7TQTh8RZnbncG dDKMLV3UqGTYsCbwHB+waFqW8JD+ah2RcMYbccc4= Message-ID: <52c08932-4f09-44f5-91b7-40812b0bea4f@ideasonboard.com> Date: Wed, 26 Jun 2024 13:52:17 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/11] drm/bridge: cdns-dsi: Wait for Clk and Data Lanes to be ready To: Aradhya Bhatia , Dmitry Baryshkov , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Jyri Sarha , Thomas Zimmermann , David Airlie , Daniel Vetter Cc: DRI Development List , Linux Kernel List , Dominik Haller , Sam Ravnborg , Thierry Reding , Kieran Bingham , Nishanth Menon , Vignesh Raghavendra , Praneeth Bajjuri , Udit Kumar , Devarsh Thakkar , Jayesh Choudhary , Jai Luthra References: <20240622110929.3115714-1-a-bhatia1@ti.com> <20240622110929.3115714-7-a-bhatia1@ti.com> From: Tomi Valkeinen Content-Language: en-US Autocrypt: addr=tomi.valkeinen@ideasonboard.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 22/06/2024 14:09, Aradhya Bhatia wrote: > Once the DSI Link and DSI Phy are initialized, the code needs to wait > for Clk and Data Lanes to be ready, before continuing configuration. > This is in accordance with the DSI Start-up procedure, found in the > Technical Reference Manual of Texas Instrument's J721E SoC[0] which > houses this DSI TX controller. > > If the previous bridge (or crtc/encoder) are configured pre-maturely, > the input signal FIFO gets corrupt. This introduces a color-shift on the > display. > > Allow the driver to wait for the clk and data lanes to get ready during > DSI enable. > > [0]: See section 12.6.5.7.3 "Start-up Procedure" in J721E SoC TRM > TRM Link: http://www.ti.com/lit/pdf/spruil1 > > Fixes: e19233955d9e ("drm/bridge: Add Cadence DSI driver") > Tested-by: Dominik Haller > Signed-off-by: Aradhya Bhatia > --- > drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c > index 426f77092341..126e4bccd868 100644 > --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c > +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c > @@ -764,7 +764,7 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge) > struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy; > unsigned long tx_byte_period; > struct cdns_dsi_cfg dsi_cfg; > - u32 tmp, reg_wakeup, div; > + u32 tmp, reg_wakeup, div, status; > int nlanes; > > if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0)) > @@ -781,6 +781,17 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge) > cdns_dsi_init_link(dsi); > cdns_dsi_hs_init(dsi); > > + /* > + * Now that the DSI Link and DSI Phy are initialized, > + * wait for the CLK and Data Lanes to be ready. > + */ > + tmp = CLK_LANE_RDY; > + for (int i = 0; i < nlanes; i++) > + tmp |= DATA_LANE_RDY(i); > + > + WARN_ON_ONCE(readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status, > + status & tmp, 100, 0)); I think an error print is more suitable than WARN_ON_ONCE(). Other than that: Reviewed-by: Tomi Valkeinen Tomi > + > writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa), > dsi->regs + VID_HSIZE1); > writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),