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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4f992d3de9sm2574010a12.14.2025.09.02.18.45.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Sep 2025 18:45:19 -0700 (PDT) Message-ID: <52c1f77a-b3b9-4c4f-90b8-1ff2ac042724@oss.qualcomm.com> Date: Wed, 3 Sep 2025 09:45:14 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/2] arm64: dts: qcom: Add display support for QCS615 RIDE board To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, xiangxu.yin@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Li Liu References: <20250827-add-display-support-for-qcs615-platform-v7-0-917c3de8f9ca@oss.qualcomm.com> <20250827-add-display-support-for-qcs615-platform-v7-2-917c3de8f9ca@oss.qualcomm.com> <0c2a4877-d63b-4650-b7d4-a06a2730c73c@oss.qualcomm.com> <4913e937-3892-42ac-8145-cc9c2364242c@oss.qualcomm.com> <7sd3rvvwnte7dub6vuywi6np7rig547ugfpu626ruufx7psrds@igqdchhianju> Content-Language: en-US From: Fange Zhang In-Reply-To: <7sd3rvvwnte7dub6vuywi6np7rig547ugfpu626ruufx7psrds@igqdchhianju> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: NXm_7xfal6DPIeLNE6H-VHlE67qbCFjw X-Proofpoint-ORIG-GUID: NXm_7xfal6DPIeLNE6H-VHlE67qbCFjw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAyNyBTYWx0ZWRfXz4Rx9cZoGPmv I1V87StV2U/D7IEbRnxcnN2hyhpeX69xNUyLj6KVghtTBTGwgZsaTrEg8VBkL7p6E7Hexdab1mJ pbI+0+zMOEAxf51l/8jTCy458bQKS9iI67gZBzqlL9wBVFHglHNnmW9pz+e8Hkd9uu1DS6zO7vt 5x909UL1HuZGFifqRYIga+jlhKQX+hKbvaWEMvF85Gy/cmoA6LwxRHYpIAKqPwF3Mb+hFwQOqy6 c9fmcYoxnfMInU59ArZ3dgUlUu4MITnO458EET9TFbezNK2K++GRIXBhsQ4Kq0qqzCCcTidAHOh Z0EOVLfK1Pg0k5fC5sNWxzrZIekE7ra0V0Q/zntEafFOvBU+90FYQ2frXH0VEMrfBhK3Pttycbi Lgp+mPBS X-Authority-Analysis: v=2.4 cv=NrDRc9dJ c=1 sm=1 tr=0 ts=68b79db2 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=-S4KrNXkqzQhTUXETMwA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-02_09,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300027 On 9/2/2025 9:56 PM, Dmitry Baryshkov wrote: > On Mon, Sep 01, 2025 at 11:23:28AM +0800, Fange Zhang wrote: >> >> >> On 8/28/2025 7:02 PM, Dmitry Baryshkov wrote: >>> On Thu, Aug 28, 2025 at 01:12:14PM +0800, Fange Zhang wrote: >>>> >>>> >>>> On 8/28/2025 12:41 PM, Dmitry Baryshkov wrote: >>>>> On Thu, Aug 28, 2025 at 10:57:41AM +0800, Fange Zhang wrote: >>>>>> >>>>>> >>>>>> On 8/28/2025 4:01 AM, Dmitry Baryshkov wrote: >>>>>>> On Wed, Aug 27, 2025 at 09:08:39PM +0800, Fange Zhang wrote: >>>>>>>> From: Li Liu >>>>>>>> >>>>>>>> Add display MDSS and DSI configuration for QCS615 RIDE board. >>>>>>>> QCS615 has a DP port, and DP support will be added in a later patch. >>>>>>>> >>>>>>>> Reviewed-by: Dmitry Baryshkov >>>>>>>> Signed-off-by: Li Liu >>>>>>>> Signed-off-by: Fange Zhang >>>>>>>> --- >>>>>>>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 150 +++++++++++++++++++++++++++++++ >>>>>>>> 1 file changed, 150 insertions(+) >>>>>>>> >>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>>>>>> index e663343df75d59481786192cde647017a83c4191..f6e0c82cf85459d8989332497ded8b6ea3670c76 100644 >>>>>>>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>>>>>> @@ -39,6 +39,76 @@ xo_board_clk: xo-board-clk { >>>>>>>> }; >>>>>>>> }; >>>>>>>> + dp-dsi0-connector { >>>>>>>> + compatible = "dp-connector"; >>>>>>>> + label = "DSI0"; >>>>>>>> + type = "mini"; >>>>>>>> + >>>>>>>> + port { >>>>>>>> + dp_dsi0_connector_in: endpoint { >>>>>>>> + remote-endpoint = <&dsi2dp_bridge_out>; >>>>>>>> + }; >>>>>>>> + }; >>>>>>>> + }; >>>>>>>> + >>>>>>>> + vreg_12p0: vreg-12p0-regulator { >>>>>>> >>>>>>> I should be more carefull when doing reviews. I thought that it was >>>>>>> pointed out already and didn't some of the obvious things... >>>>>>> >>>>>>> First of all, the nodes are sorted. By the name, not by the label. >>>>>>> Second, there are already regulators in this file. Why are the new nodes >>>>>>> not following the existing pattern and why are they not placed at a >>>>>>> proper place? >>>>>> >>>>>> Initially, we referred to https://patchwork.kernel.org/project/linux-arm-msm/patch/20250604071851.1438612-3-quic_amakhija@quicinc.com/ >>>>>> as a reference, but its node ordering seems a bit unconventional. >>>>>> >>>>>> Would this revised ordering be acceptable? >>>>>> >>>>>> ... >>>>>> + dp-dsi0-connector >>>>>> >>>>>> vreg_conn_1p8: regulator-conn-1p8 >>>>>> vreg_conn_pa: regulator-conn-pa >>>>>> regulator-usb2-vbus >>>>> >>>>> So... Existing regulator nodes have the name of 'regulator-foo-bar'. >>>>> >>>>>> >>>>>> + vreg_12p0: vreg-12p0-regulator >>>>>> + vreg_1p0: vreg-1p0-regulator >>>>>> + vreg_1p8: vreg-1p8-regulator >>>>>> + vreg_3p0: vreg-3p0-regulator >>>>>> + vreg_5p0: vreg-5p0-regulator >>>>> >>>>> While yours use 'vreg-baz-regulator'. Why? Don't blindly c&p data from >>>>> other platforms. >>>> >>>> Got it, The revised format will be: >>>> >>>> + vreg_12p0: regulator-vreg-12p0 >>>> + vreg_1p0: regulator-vreg-1p0 >>>> + vreg_1p8: regulator-vreg-1p8 >>>> + vreg_3p0: regulator-vreg-3p0 >>>> + vreg_5p0: regulator-vreg-5p0 >>>> >>>> Let me know if you have any further suggestions. >>> >>> What's the name of power rail in the schematics? vreg-Np0? >> >> I reviewed the Ride board schematics and found the following power rail >> mappings: >> >> VREG_1P0 -> DSI0_DVDD10 / DSI0_AVDD10 -> ANX7625 AVDD10 / DVDD10 >> VREG_1P8 -> DSI0_AVDD18 -> ANX7625 AVDD18 >> VREG_S4A_1P8 -> DSI0_DVDD18 -> ANX7625 DVDD18 >> VIDEO_OUT_VREG_3P3 -> DSI0_AVDD30 -> ANX7625 AVDD30 > > Then it looks like regulator-vreg-NpM is okay Got it, I'll update v8 today following this format. Thanks! > >> >> would the current approach also be acceptable? >> or we need configure the power supplies strictly according to this mapping. >> Appreciate your guidance. >> >>> >>> >> >