From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 906C8423780 for ; Fri, 24 Jul 2026 13:15:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784898933; cv=none; b=pSNMZO3HKc4+B6kSsZG6nPeFPKw8HtLcZRHq4bHveXt9PGHkKJ6dE2/EFJP//d8lCMz7uan8jmtrkLxq6U8ataw831oNBarkayCv0k94ErqiTzdHKuJdLokeVJ8weihRfJvijy3dwZOCb/0yvCUlbmcnQQi1CLNxI7K5xaLF39M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784898933; c=relaxed/simple; bh=mytmLjw00SKza60sJL16TQSBEWqZ6rjTnD1St8aeA/k=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=PC3cjK2PMM+ZyTONErCCcempb3CagwPUdtz+ZfsOjj+XjCLxGfSpd1xXxdsCO4Mew4RDcjDI9EFuLJgKTZvwjDvL1aq7+Aa8h4FNurZ4O/E0x9mXtmkw/JPviZxTGU0yv5M2hjNLqcNi9+qy7zpp5VJJWRmm+kJb1vD0BiIqxqw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=FSyn1G21; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="FSyn1G21" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-5b014810feeso63040e87.1 for ; Fri, 24 Jul 2026 06:15:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1784898929; x=1785503729; darn=vger.kernel.org; h=content-transfer-encoding:content-type:in-reply-to:from:references :cc:to:subject:user-agent:mime-version:date:message-id:from:to:cc :subject:date:message-id:reply-to:content-type; bh=kA59vUE7m4ECPboC5exULRzAZyferaA5ztYUd5SayZg=; b=FSyn1G21Ijczzqi8Gzdp1IyXXFNRcDfgjRLtpg/fEUBRFqm1glpG2gdo0rXVfJcIcj AIkjL2Er5ZXS7dlk3GWrKeaxbG9QoZxyZDKBPFJM4ngvlbmrldHR2QV86m+HTsJBiF2H 6Y1KQdTIIcw/DAfwSpwqEFok0ttuCU69m1kkVwOBCsnqnd1QtLpnANC0JaNquJn2Pt+6 4LdKxf+zSoVBHs+kOFkmP4V6acyDMpfVvzs45V4FgQ8O8GKbgos7R7o6kDV/7w5oh7H2 uJzIY13oGqSq6h7cdYbTd8UBF8twMO/Egfoy0AZPsY7sXkOppu3aIJ1FoMR9FzM0ttzH 4rbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784898929; x=1785503729; h=content-transfer-encoding:content-type:in-reply-to:from:references :cc:to:subject:user-agent:mime-version:date:message-id:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=kA59vUE7m4ECPboC5exULRzAZyferaA5ztYUd5SayZg=; b=qOW73IRTshruUvLQ0Z4n9HVucQQ3sj88DrAi6fzxEQVi/gnhGczPtp5LU7fPAbADk+ nxCnYMGwO4SPGCSm6ayyGvlr1QklDOA6tK1zOTxttqB52S1CvWgm2orPBqJLHQrvT2OH zrhlC1YDuw4nUZrpXVXCMfLlEtxeR4uH0Xk4KWNmxeBrFm9NSsc5m8lDhAhaIkYaHem3 WFgbwt/dYPab0RHhCOW8B9xQILZmsiM1IyFrvXqWiXo4sSuORzhN1ev1FgGfqvGpLZ0S 6kYQiniunfp/apvibMgu8IUBr1Jm9UDosDL5jvmdm7KO5KEfwKH5C9D/DeHEKjF8sWri ib+Q== X-Forwarded-Encrypted: i=1; AHgh+Rq/2p4MBsyLCLYh1A5g7qV2SIPDBHJedQCU7F9qSz9yywSgc+fRL5NNUGcZ7h69PldkUKSK+x98zesVmbA=@vger.kernel.org X-Gm-Message-State: AOJu0YwYwHSyl8CYJQudBgq+QldKc0H3ZlCvl77lp3dh04jo/wNaz06S HIDQflomFAAUfTl+SeBHv40Eym2YlBN2CzT7URTNxjE0BDoBkrxHnf0/rUHJvkL4g2s= X-Gm-Gg: AR+sD10pIutdUp/r9C+PDVyGx+Z6cAQtdWJfFNvIWT9iUJc2JqvoNHv3WsccTa1eofT E2PSwu18NBs97CptNXm2RWQdDEChjT4I9alkeYqzsmmr4N3tM0T/WEZbNxKpdJQzMZ0B9mpBOJa fV1sHP84cVUvasJYJ1OKclgjm5Dc9ZWBL3bUAEr3H6YFABgHxS+0IrZOo+uUXezqoxWTngbWK/I Iy0Pl1rhPDJB5FItjFsO5Zf1DlyOgOHqubI+Wyy5kZEQLPHCUI/QVJe1eN/K++1CozjM7mld5P4 VCSugy2ugpSgmR2GCfCURNPiqRpswLpX2piWuDaaQhfWJ4i83WrRGalWvRb1WLwfjIAZpkdGQTZ HZiOMcOS11HFLqmzO+7AomwyvSoo+6Kga/nXkTTrNSiV4hGVgk2uze/xdB/yLznN9deIjEmwdHU WunEfSjYW3xP+5SEiV+xhS2QZLSYtIiCzHkGobKbYYD+63hguldG/SQDuqyidPJOEBqs8= X-Received: by 2002:a05:6512:3e01:b0:5b1:5e89:30f6 with SMTP id 2adb3069b0e04-5b2b2f6efb3mr856162e87.3.1784898929451; Fri, 24 Jul 2026 06:15:29 -0700 (PDT) Received: from [192.168.1.100] (91-159-24-186.elisa-laajakaista.fi. [91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2a9e4611dsm1545595e87.67.2026.07.24.06.15.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 06:15:26 -0700 (PDT) Message-ID: <52c6ea74-5938-465d-ad22-4192eef658a1@linaro.org> Date: Fri, 24 Jul 2026 16:15:25 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/17] media: i2c: os05b10: split common and mode-specific init registers To: Tarang Raval , sakari.ailus@linux.intel.com, mehdi.djait@linux.intel.com Cc: Himanshu Bhavani , Elgin Perumbilly , Mauro Carvalho Chehab , Hans Verkuil , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260718200912.16001-1-tarang.raval@siliconsignals.io> <20260718200912.16001-5-tarang.raval@siliconsignals.io> From: Vladimir Zapolskiy In-Reply-To: <20260718200912.16001-5-tarang.raval@siliconsignals.io> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/18/26 23:08, Tarang Raval wrote: > Separate common initialization registers from mode-specific settings. > Move resolution-dependent registers into a per-mode register list and > program them during stream enable. > > Signed-off-by: Tarang Raval > --- > drivers/media/i2c/os05b10.c | 96 ++++++++++++++++++++++++------------- > 1 file changed, 63 insertions(+), 33 deletions(-) > > diff --git a/drivers/media/i2c/os05b10.c b/drivers/media/i2c/os05b10.c > index 96395cd7a2ca..12c4e2610d6f 100644 > --- a/drivers/media/i2c/os05b10.c > +++ b/drivers/media/i2c/os05b10.c > @@ -142,16 +142,13 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { OS05B10_REG_EXPOSURE_SHORT, 0x000020 }, > { CCI_REG8(0x3600), 0x4d }, > { CCI_REG8(0x3601), 0x08 }, > - { CCI_REG8(0x3610), 0x87 }, > { CCI_REG8(0x3611), 0x24 }, > { CCI_REG8(0x3614), 0x4c }, > - { CCI_REG8(0x3620), 0x0c }, > { CCI_REG8(0x3632), 0x80 }, > { CCI_REG8(0x3633), 0x00 }, > { CCI_REG8(0x3636), 0xcc }, > { CCI_REG8(0x3637), 0x27 }, > { CCI_REG8(0x3660), 0x00 }, > - { CCI_REG8(0x3662), 0x10 }, > { CCI_REG8(0x3665), 0x00 }, > { CCI_REG8(0x3666), 0x00 }, > { CCI_REG8(0x366a), 0x14 }, > @@ -235,7 +232,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x370f), 0x1c }, > { CCI_REG8(0x3710), 0x00 }, > { CCI_REG8(0x3713), 0x00 }, > - { CCI_REG8(0x3714), 0x24 }, > { CCI_REG8(0x3716), 0x24 }, > { CCI_REG8(0x371a), 0x1e }, > { CCI_REG8(0x3724), 0x09 }, > @@ -244,7 +240,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x3730), 0xe1 }, > { CCI_REG8(0x3735), 0x80 }, > { CCI_REG8(0x3739), 0x10 }, > - { CCI_REG8(0x373f), 0xb0 }, > { CCI_REG8(0x3740), 0x28 }, > { CCI_REG8(0x3741), 0x21 }, > { CCI_REG8(0x3742), 0x21 }, > @@ -290,8 +285,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x37ac), 0xa0 }, > { CCI_REG8(0x37be), 0x0a }, > { CCI_REG8(0x37bb), 0x02 }, > - { CCI_REG8(0x37bf), 0x05 }, > - { CCI_REG8(0x37c2), 0x04 }, > { CCI_REG8(0x37c4), 0x11 }, > { CCI_REG8(0x37c5), 0x80 }, > { CCI_REG8(0x37c6), 0x14 }, > @@ -300,7 +293,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x37cd), 0x17 }, > { CCI_REG8(0x37ce), 0x01 }, > { CCI_REG8(0x37d8), 0x02 }, > - { CCI_REG8(0x37d9), 0x08 }, > { CCI_REG8(0x37dc), 0x01 }, > { CCI_REG8(0x37e0), 0x0c }, > { CCI_REG8(0x37e1), 0x20 }, > @@ -313,25 +305,10 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x37f5), 0x00 }, > { CCI_REG8(0x37f6), 0x00 }, > { CCI_REG8(0x37f7), 0x00 }, > - { OS05B10_REG_X_ADDR_START, 0x0130 }, > - { OS05B10_REG_Y_ADDR_START, 0x0000 }, > - { OS05B10_REG_X_ADDR_END, 0x0b5f }, > - { OS05B10_REG_Y_ADDR_END, 0x07a7 }, > - { OS05B10_REG_X_OUTPUT_SIZE, 0x0a20 }, > - { OS05B10_REG_Y_OUTPUT_SIZE, 0x0798 }, > - { OS05B10_REG_HTS, 0x06d0 }, > - { OS05B10_REG_ISP_X_WIN, 0x0008 }, > - { OS05B10_REG_ISP_Y_WIN, 0x0008 }, > - { OS05B10_REG_X_INC_ODD, 0x01 }, > - { OS05B10_REG_X_INC_EVEN, 0x01 }, > - { OS05B10_REG_Y_INC_ODD, 0x01 }, > - { OS05B10_REG_Y_INC_EVEN, 0x01 }, > { CCI_REG8(0x3818), 0x00 }, > { CCI_REG8(0x3819), 0x00 }, > { CCI_REG8(0x381a), 0x00 }, > { CCI_REG8(0x381b), 0x01 }, > - { OS05B10_REG_FORMAT1, 0x88 }, > - { OS05B10_REG_FORMAT2, 0x00 }, > { CCI_REG8(0x3822), 0x12 }, > { CCI_REG8(0x3823), 0x08 }, > { CCI_REG8(0x3824), 0x00 }, > @@ -341,7 +318,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x3829), 0x03 }, > { CCI_REG8(0x382a), 0x00 }, > { CCI_REG8(0x382b), 0x00 }, > - { CCI_REG8(0x3832), 0x08 }, > { CCI_REG8(0x3838), 0x00 }, > { CCI_REG8(0x3839), 0x00 }, > { CCI_REG8(0x383a), 0x00 }, > @@ -362,26 +338,19 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x38a7), 0x04 }, > { CCI_REG8(0x38b8), 0x02 }, > { CCI_REG8(0x3c80), 0x3e }, > - { CCI_REG8(0x3c86), 0x01 }, > { CCI_REG8(0x3c87), 0x02 }, > { CCI_REG8(0x389c), 0x00 }, > { CCI_REG8(0x3ca2), 0x0c }, > { CCI_REG8(0x3d85), 0x1b }, > - { CCI_REG8(0x3d8c), 0x01 }, > { CCI_REG8(0x3d8d), 0xe2 }, > { CCI_REG8(0x3f00), 0xcb }, > - { CCI_REG8(0x3f03), 0x08 }, > { CCI_REG8(0x3f9e), 0x07 }, > { CCI_REG8(0x3f9f), 0x04 }, > { CCI_REG8(0x4000), 0xf3 }, > { CCI_REG8(0x4002), 0x00 }, > { CCI_REG8(0x4003), 0x40 }, > - { CCI_REG8(0x4008), 0x02 }, > - { CCI_REG8(0x4009), 0x0d }, > - { CCI_REG8(0x400a), 0x01 }, > { CCI_REG8(0x400b), 0x00 }, > { CCI_REG8(0x4040), 0x00 }, > - { CCI_REG8(0x4041), 0x07 }, > { CCI_REG8(0x4090), 0x14 }, > { CCI_REG8(0x40b0), 0x01 }, > { CCI_REG8(0x40b1), 0x01 }, > @@ -401,7 +370,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x4305), 0x83 }, > { CCI_REG8(0x4306), 0x21 }, > { CCI_REG8(0x430d), 0x00 }, > - { CCI_REG8(0x4505), 0xc4 }, > { CCI_REG8(0x4506), 0x00 }, > { CCI_REG8(0x4507), 0x60 }, > { CCI_REG8(0x4803), 0x00 }, > @@ -413,7 +381,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x481f), 0x30 }, > { CCI_REG8(0x4825), 0x34 }, > { CCI_REG8(0x4829), 0x64 }, > - { CCI_REG8(0x4837), 0x12 }, > { CCI_REG8(0x484b), 0x07 }, > { CCI_REG8(0x4883), 0x36 }, > { CCI_REG8(0x4885), 0x03 }, > @@ -446,6 +413,42 @@ static const struct cci_reg_sequence os05b10_common_regs[] = { > { CCI_REG8(0x3222), 0x03 }, > }; > > +static const struct cci_reg_sequence mode_2592_1944_regs[] = { > + { OS05B10_REG_X_ADDR_START, 0x0130 }, > + { OS05B10_REG_Y_ADDR_START, 0x0000 }, > + { OS05B10_REG_X_ADDR_END, 0x0b5f }, > + { OS05B10_REG_Y_ADDR_END, 0x07a7 }, > + { OS05B10_REG_X_OUTPUT_SIZE, 0x0a20 }, > + { OS05B10_REG_Y_OUTPUT_SIZE, 0x0798 }, > + { OS05B10_REG_HTS, 0x06d0 }, > + { OS05B10_REG_ISP_X_WIN, 0x0008 }, > + { OS05B10_REG_ISP_Y_WIN, 0x0008 }, > + { OS05B10_REG_X_INC_ODD, 0x01 }, > + { OS05B10_REG_X_INC_EVEN, 0x01 }, > + { OS05B10_REG_Y_INC_ODD, 0x01 }, > + { OS05B10_REG_Y_INC_EVEN, 0x01 }, > + { OS05B10_REG_FORMAT1, 0x88 }, > + { OS05B10_REG_FORMAT2, 0x00 }, > + { CCI_REG8(0x3610), 0x87 }, > + { CCI_REG8(0x3620), 0x0c }, > + { CCI_REG8(0x3662), 0x10 }, > + { CCI_REG8(0x3714), 0x24 }, > + { CCI_REG8(0x373f), 0xb0 }, > + { CCI_REG8(0x37bf), 0x05 }, > + { CCI_REG8(0x37c2), 0x04 }, > + { CCI_REG8(0x37d9), 0x08 }, > + { CCI_REG8(0x3832), 0x08 }, > + { CCI_REG8(0x3c86), 0x01 }, > + { CCI_REG8(0x3d8c), 0x01 }, > + { CCI_REG8(0x3f03), 0x08 }, > + { CCI_REG8(0x4008), 0x02 }, > + { CCI_REG8(0x4009), 0x0d }, > + { CCI_REG8(0x400a), 0x01 }, > + { CCI_REG8(0x4041), 0x07 }, > + { CCI_REG8(0x4505), 0xc4 }, > + { CCI_REG8(0x4837), 0x12 }, > +}; > + > struct os05b10 { > struct device *dev; > struct regmap *cci; > @@ -468,6 +471,11 @@ struct os05b10 { > u32 data_lanes; > }; > > +struct os05b10_reg_list { > + u32 num_of_regs; > + const struct cci_reg_sequence *regs; > +}; > + > struct os05b10_mode { > u32 width; > u32 height; > @@ -475,6 +483,7 @@ struct os05b10_mode { > u32 hts; > u32 exp; > u8 bpp; > + struct os05b10_reg_list reg_list; > }; > > static const struct os05b10_mode supported_modes_10bit[] = { > @@ -485,6 +494,10 @@ static const struct os05b10_mode supported_modes_10bit[] = { > .hts = 1744, > .exp = 1944, > .bpp = 10, > + .reg_list = { > + .num_of_regs = ARRAY_SIZE(mode_2592_1944_regs), > + .regs = mode_2592_1944_regs, > + }, > }, > }; > > @@ -654,8 +667,16 @@ static int os05b10_enable_streams(struct v4l2_subdev *sd, > u32 pad, u64 streams_mask) > { > struct os05b10 *os05b10 = to_os05b10(sd); > + const struct os05b10_reg_list *reg_list; > + const struct v4l2_mbus_framefmt *fmt; > + const struct os05b10_mode *mode; > int ret; > > + fmt = v4l2_subdev_state_get_format(state, 0); > + mode = v4l2_find_nearest_size(supported_modes_10bit, > + ARRAY_SIZE(supported_modes_10bit), width, > + height, fmt->width, fmt->height); > + > ret = pm_runtime_resume_and_get(os05b10->dev); > if (ret < 0) > return ret; > @@ -668,6 +689,15 @@ static int os05b10_enable_streams(struct v4l2_subdev *sd, > goto err_rpm_put; > } > > + /* Write sensor mode registers */ > + reg_list = &mode->reg_list; > + ret = cci_multi_reg_write(os05b10->cci, reg_list->regs, > + reg_list->num_of_regs, NULL); > + if (ret) { > + dev_err(os05b10->dev, "fail to write initial registers\n"); > + goto err_rpm_put; > + } > + > /* Apply customized user controls */ > ret = __v4l2_ctrl_handler_setup(os05b10->sd.ctrl_handler); > if (ret) Reviewed-by: Vladimir Zapolskiy -- Best wishes, Vladimir