From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9368D372ED6 for ; Fri, 3 Apr 2026 07:56:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775202974; cv=none; b=aNCfm/qi3biSFvGbJrKnvMS1d7y3FmE+6R7MTBf/Ox61L5izx5X6udY/AsN+aAg+1smz04ymNkyxttgvbl+m16r4uMnrEXWD8WDa9lybOEAs70YUAM21uwk8/g7hQ0ECCdP7X3StAEMj+ubJ0ofdnKyiSbYeUEOC5Q5MWjGHHVE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775202974; c=relaxed/simple; bh=QWX7ACF7MfXiV09SgQFh5qTQ4GTnVw2pFbefikFwxHM=; h=Date:From:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=Q9R0Uo5BvmG9aznQGay7mS86i+BFtm0YzvPO86JqpP4N6FKv7KaLp3BsONyCxCS1XnwhIE8rWMuHGazx/MfI+TOnJ7WRCPNT6T4pPIo3nE1Zho+/7+LscRrM072Zxqd/jTzzJQ5Q8nV7a5EAdZ4GJWDza4ZqBGmxFLxkY8sADtw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RYkX0eCL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RYkX0eCL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C6966C4CEF7; Fri, 3 Apr 2026 07:56:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775202974; bh=QWX7ACF7MfXiV09SgQFh5qTQ4GTnVw2pFbefikFwxHM=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=RYkX0eCLaOz2UKmv8BN/qj5xcBj3JvnnYLQ3uxqHcQiX8WGcCmlhECw883H/ppOy/ D0vXDvg7uuwOOMugCJwUkuaHu5pDU9F3QOxwLNuG3QYSHdgPj7j5BR+Xkm4xBFjBkw NzCUiGyK/VMUrPUBs7K/zxhLnO7cI/xNsWZWusOTm4j7P0zxLWRjC1gMv7cifHGmjR tpcp+xp/khyaZ3iQaki04GhWefZrtrxgsTLPSAGeTL2ix5M+0pd5nOnMztLtroE+rB gTCxXHzEmF2v9PsgeSjkVj/4CvDmUA41Mjxn6SfufPVdtfN7EdFa2lTKejbBe0FSql A/kpWBcbLRGWA== Date: Fri, 3 Apr 2026 01:56:12 -0600 (MDT) From: Paul Walmsley To: Andreas Schwab cc: Michael Neuling , pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, debug@rivosinc.com, thecharlesjenkins@gmail.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] riscv: ptrace: avoid BIT() in UAPI header In-Reply-To: Message-ID: <52d5b30d-c15e-2dca-110d-d1ff78898c23@kernel.org> References: <20260330024248.449292-1-mikey@neuling.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-1642680336-1775202974=:2029891" This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-1642680336-1775202974=:2029891 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Mon, 30 Mar 2026, Andreas Schwab wrote: > On Mär 30 2026, Michael Neuling wrote: > > > BIT() is not available in UAPI headers — the installed linux/bits.h > > (UAPI version) does not define it. Replace BIT() with open-coded > > (1UL << x) which is the standard practice for UAPI headers, and drop > > the linux/bits.h include that was added by commit 98545620b0 ("riscv: > > ptrace: Fix BIT() compilation issues"). > > There is also the _BITUL macro, which may be preferable. Thanks everyone. Below is what I ended up with. I'll drop Charlie's two patches to avoid churn. - Paul From: Paul Walmsley Date: Thu, 2 Apr 2026 17:18:03 -0600 Subject: [PATCH] riscv: use _BITUL macro rather than BIT() in ptrace uapi and kselftests Fix the build of non-kernel code that includes the RISC-V ptrace uapi header, and the RISC-V validate_v_ptrace.c kselftest, by using the _BITUL() macro rather than BIT(). BIT() is not available outside the kernel. Based on patches and comments from Charlie Jenkins, Michael Neuling, and Andreas Schwab. Fixes: 30eb191c895b ("selftests: riscv: verify ptrace rejects invalid vector csr inputs") Fixes: 2af7c9cf021c ("riscv/ptrace: expose riscv CFI status and state via ptrace and in core files") Cc: Andreas Schwab Cc: Michael Neuling Cc: Charlie Jenkins Link: https://patch.msgid.link/20260330024248.449292-1-mikey@neuling.org Link: https://lore.kernel.org/linux-riscv/20260309-fix_selftests-v2-1-9d5a553a531e@gmail.com/ Link: https://lore.kernel.org/linux-riscv/20260309-fix_selftests-v2-3-9d5a553a531e@gmail.com/ Signed-off-by: Paul Walmsley --- arch/riscv/include/uapi/asm/ptrace.h | 13 +++++++------ .../selftests/riscv/vector/validate_v_ptrace.c | 4 ++-- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 18988a5f1a63..70a74adad914 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -9,6 +9,7 @@ #ifndef __ASSEMBLER__ #include +#include #define PTRACE_GETFDPIC 33 @@ -138,12 +139,12 @@ struct __sc_riscv_cfi_state { #define PTRACE_CFI_SS_LOCK_BIT 4 #define PTRACE_CFI_SS_PTR_BIT 5 -#define PTRACE_CFI_LP_EN_STATE BIT(PTRACE_CFI_LP_EN_BIT) -#define PTRACE_CFI_LP_LOCK_STATE BIT(PTRACE_CFI_LP_LOCK_BIT) -#define PTRACE_CFI_ELP_STATE BIT(PTRACE_CFI_ELP_BIT) -#define PTRACE_CFI_SS_EN_STATE BIT(PTRACE_CFI_SS_EN_BIT) -#define PTRACE_CFI_SS_LOCK_STATE BIT(PTRACE_CFI_SS_LOCK_BIT) -#define PTRACE_CFI_SS_PTR_STATE BIT(PTRACE_CFI_SS_PTR_BIT) +#define PTRACE_CFI_LP_EN_STATE _BITUL(PTRACE_CFI_LP_EN_BIT) +#define PTRACE_CFI_LP_LOCK_STATE _BITUL(PTRACE_CFI_LP_LOCK_BIT) +#define PTRACE_CFI_ELP_STATE _BITUL(PTRACE_CFI_ELP_BIT) +#define PTRACE_CFI_SS_EN_STATE _BITUL(PTRACE_CFI_SS_EN_BIT) +#define PTRACE_CFI_SS_LOCK_STATE _BITUL(PTRACE_CFI_SS_LOCK_BIT) +#define PTRACE_CFI_SS_PTR_STATE _BITUL(PTRACE_CFI_SS_PTR_BIT) #define PRACE_CFI_STATE_INVALID_MASK ~(PTRACE_CFI_LP_EN_STATE | \ PTRACE_CFI_LP_LOCK_STATE | \ diff --git a/tools/testing/selftests/riscv/vector/validate_v_ptrace.c b/tools/testing/selftests/riscv/vector/validate_v_ptrace.c index 3589549f7228..7ae6fede496f 100644 --- a/tools/testing/selftests/riscv/vector/validate_v_ptrace.c +++ b/tools/testing/selftests/riscv/vector/validate_v_ptrace.c @@ -346,8 +346,8 @@ FIXTURE_TEARDOWN(v_csr_invalid) { } -#define VECTOR_1_0 BIT(0) -#define XTHEAD_VECTOR_0_7 BIT(1) +#define VECTOR_1_0 _BITUL(0) +#define XTHEAD_VECTOR_0_7 _BITUL(1) #define vector_test(x) ((x) & VECTOR_1_0) #define xthead_test(x) ((x) & XTHEAD_VECTOR_0_7) -- 2.51.0 --8323329-1642680336-1775202974=:2029891--