From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Prabhakar <prabhakar.csengg@gmail.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Claudiu Beznea" <claudiu.beznea.uj@bp.renesas.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>
Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v3 1/4] dt-bindings: PCI: renesas,r9a08g045-pcie: Add RZ/V2H(P) support
Date: Tue, 2 Jun 2026 10:58:25 +0300 [thread overview]
Message-ID: <52d6e1e0-ee68-4932-af20-b353655bac77@tuxon.dev> (raw)
In-Reply-To: <20260520164823.436992-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
On 5/20/26 19:48, Prabhakar wrote:
> From: Lad Prabhakar<prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support for the PCIe controller found on the Renesas RZ/V2H(P) SoC.
>
> The RZ/V2H(P) controller is similar to the RZ/G3E variant but includes
> additional registers and configuration bits for PCIe lane control. It
> supports multilink operation configured as either a single x4 link
> or two independent x2 link controllers.
>
> Unlike earlier SoCs supported by this driver which only feature a single
> PCIe controller, the RZ/V2H(P) SoC implements two controllers. Both
> instances rely on the system controller (SYSC) for configuration, but
> the required registers reside at different offsets for each controller.
>
> To correctly identify the controller instance and map the corresponding
> system controller registers, update the "renesas,sysc" property to a
> phandle-array. For the RZ/V2H(P) SoC, require an accompanying cell to
> specify the controller instance index (0 or 1). For all earlier SoCs,
> strictly restrict the property to a single phandle with zero argument
> cells.
>
> Additionally, make the "num-lanes" property mandatory for this SoC and
> restrict its values according to the hardware capabilities.
>
> Signed-off-by: Lad Prabhakar<prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
next prev parent reply other threads:[~2026-06-02 7:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-20 16:48 [PATCH v3 0/4] Add PCIe support for RZ/V2H(P) SoC Prabhakar
2026-05-20 16:48 ` [PATCH v3 1/4] dt-bindings: PCI: renesas,r9a08g045-pcie: Add RZ/V2H(P) support Prabhakar
2026-06-01 23:22 ` Rob Herring (Arm)
2026-06-02 7:58 ` Claudiu Beznea [this message]
2026-05-20 16:48 ` [PATCH v3 2/4] PCI: rzg3s-host: Use shared reset controls for power domain resets Prabhakar
2026-06-02 7:58 ` Claudiu Beznea
2026-05-20 16:48 ` [PATCH v3 3/4] PCI: rzg3s-host: Prepare System Controller handling for multiple controllers Prabhakar
2026-06-02 7:59 ` Claudiu Beznea
2026-05-20 16:48 ` [PATCH v3 4/4] PCI: rzg3s-host: Add support for RZ/V2H(P) SoC Prabhakar
2026-06-02 8:00 ` Claudiu Beznea
2026-06-02 19:41 ` Lad, Prabhakar
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