From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751175AbbEFLkC (ORCPT ); Wed, 6 May 2015 07:40:02 -0400 Received: from mout.kundenserver.de ([212.227.17.10]:54932 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750756AbbEFLj7 (ORCPT ); Wed, 6 May 2015 07:39:59 -0400 Date: Wed, 6 May 2015 13:39:56 +0200 (CEST) From: Johannes Thoma Reply-To: Johannes Thoma To: linux-kernel@vger.kernel.org Message-ID: <530602563.487644.1430912396946.JavaMail.open-xchange@oxbaltgw03.schlund.de> Subject: Question about cacheline aligned memory for DMA transfers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Priority: 3 Importance: Medium X-Mailer: Open-Xchange Mailer v7.6.0-Rev38 X-Originating-Client: com.openexchange.ox.gui.dhtml X-Provags-ID: V03:K0:EpH1DbxSjEnexxeYpDER/vNoJgzt5EhCpWSXLLt1X+dWWgyeX8B BV2SJyXPa4ZTdGVfchJPcxKNzNHoIa/jcBu/mtc9zEEWHFmWxn1N/2rfNqAK6SzjkP3jD2L vm0sWaeEMWCM0EwvVxQFO0dErGwIrXfOtxmQc5veGrr/e4w7+a5zrmOICoIE1ZwI+rK0maB EevsBKDyQNM2CC5xrQFLw== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear list, I am working on a memory corruption problem with a patched 2.6.21 kernel in the USB driver. In order to better understand the problem I would like to ask how current kernels handle the case where the same cacheline is used for a DMA-able object and another object. Does kmalloc return only memory that is cache line aligned? If not, do all architectures handle cache line misalign ed dma accesses correctly like the powerpc (although not yet in 2.6.21) architecture does? Thanks for any insights. - Johannes PS: Please CC me I am not on the list.