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[89.162.31.138]) by smtp.gmail.com with ESMTPSA id a12-20020a056512200c00b00489e38c4fc4sm3265799lfb.276.2022.07.19.09.00.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Jul 2022 09:00:55 -0700 (PDT) Message-ID: <53242a5b-0ba0-71c6-3b6c-e3a628b7eda1@linaro.org> Date: Tue, 19 Jul 2022 18:00:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] regmap: support regmap_field_write() on non-readable fields Content-Language: en-US From: Krzysztof Kozlowski To: Mark Brown Cc: Charles Keepax , Greg Kroah-Hartman , "Rafael J. Wysocki" , linux-kernel@vger.kernel.org, Srinivas Kandagatla , Kuninori Morimoto , Bjorn Andersson References: <20220719121446.375095-1-krzysztof.kozlowski@linaro.org> <20220719125401.GA92394@ediswmail.ad.cirrus.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/07/2022 16:30, Krzysztof Kozlowski wrote: > On 19/07/2022 15:41, Mark Brown wrote: >> On Tue, Jul 19, 2022 at 03:13:11PM +0200, Krzysztof Kozlowski wrote: >>> On 19/07/2022 14:54, Charles Keepax wrote: >> >>>> I think this will break other valid use-cases, regmap_readable (I >>>> believe) returns if the register is physically readable, however >>>> it should still be possible to use update bits if the register is >>>> in the cache even if it can't physically be read. So really you >>>> need to fall into this path if it is readable or in the cache. >> >>> But what type of real use case this would be trying to solve? Either >>> register is readable or not. The presence of cache is just optimization >>> and does not change the fact that we cannot read from register thus no >>> need to go via updates. >> >> The original reason for creating the cache code was to simulate >> readability on devices that have no read support at all (think 7x9 >> format I2C devices) so we can have things like helpers to map bitfields >> directly to subsystems (like ASoC uses extensively). The fact that it >> also improves performance when the hardware does support reads is nice >> too of course. >> >>>> Which does I guess also raise the question if your problem would >>>> be better solved with caching the register? >> >>> And how the value would appear in the cache? Since register cannot be >>> read, I expect the cache to be filled on first update. First update >>> would be read+write, so we are stuck again. >> >> This is one reason we allow cache defaults to be specified (it was the >> original reason, we later started using them to optimise out I/O during >> resyncs). > > Thanks Mark and Charles. Let me try the cache. cache + forced write works for me, so I guess this patch is not really necessary. Best regards, Krzysztof