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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=FqI1OWrq c=1 sm=1 tr=0 ts=6a831715 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=sndJhVXln6Iqe1BNRX4A:9 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-ORIG-GUID: 2BZDqu989BVO9H4pjcJcR_U3eFmmWtu7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE3MDEwOSBTYWx0ZWRfX1Ct20CJEps5K rk/t7Pt+NGQLiT8w7cQu2nze2nsP3wJy+2IeyZvtrmM8WJoqqvCbiVMA5Ngg0O4eeBavPIO4uT4 iYoJENzF1HirCXF95WtGSW+HYdBe6WWuA/yU4twUkw23PSQT1kPNsvk3Sj7bs/CZHy8L7dr/ld/ +ijGrC3209NpJtknB0miP/PaiQu+iXDNYQhYzvNVmm9v5Kv/GW253GMd9nJaObvzK/pUYjm41Eh bMiCpDhfdX1/ZH/MFkQj0rhOLgVymnTxVRRy2zu32RZG/hcg9mFqEQp0Uu9hYxoKchmK+F/rmuX hrb0n1gYc9Fv3cbQKIJ/AefjPCujXfL34R3gIqV1MOU6T2hRUxbbKLO/L67Tk4qaVU2L7KhFoWZ 6ew/QCFxf7iGGQEdc1ruXxOEJFd+Amy5nvL0s4o4FoixDU6NEVDqDbm2FfXwwkihu8d0NhNVRVK f8VYYVOiwdmimkqld1w== X-Proofpoint-GUID: 2BZDqu989BVO9H4pjcJcR_U3eFmmWtu7 X-Proofpoint-Spam-Info: AW1haW4tMjYwODE3MDEwOSBTYWx0ZWRfXyrDMF1pkZ7Gg 5MVbj71Pgsf4qVKkEaPMR/Lzkxxef0roZJdNhAiNyRzZEEG8Y70NbupNLMCZ7DUJYNUYWJXhrgC CY24XrNbCcRoa5hgzXY+BTtPhWWB9k0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-17_01,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608170109 On 8/13/26 9:44 AM, Yongxing Mou wrote: > > > On 7/20/2026 4:49 PM, Konrad Dybcio wrote: >> On 7/20/26 10:43 AM, Yongxing Mou wrote: >>> Kaanapali (SM8750) and Glymur use two display power domains. >>> CORE_GDSC powers the main display hardware while INT2_GDSC >>> powers a subset of SSPP blocks. >> >> Can they operate independently? Does INT2_GDSC need to be >> powered on after CORE_GDSC? >> > On Kaanapali, my understanding is that CORE_GDSC and INT2_GDSC should generally track the same state, except that INT2_GDSC may be powered down when SSPP1 (VIG2/VIG3/DMA5) is unused. Is the MDSS any useful if *only* INT2_GDSC is enabled? Can the INT2_GDSC be enabled itself if CORE_GDSC is off? Konrad