From: Dave Jiang <dave.jiang@intel.com>
To: Neeraj Kumar <s.neeraj@samsung.com>,
linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev,
linux-kernel@vger.kernel.org, gost.dev@samsung.com
Cc: a.manzanares@samsung.com, vishak.g@samsung.com, neeraj.kernel@gmail.com
Subject: Re: [PATCH V2 05/20] nvdimm/region_label: Add region label updation routine
Date: Fri, 15 Aug 2025 14:55:40 -0700 [thread overview]
Message-ID: <534936cc-4ecc-46e5-8196-bc3992e086ab@intel.com> (raw)
In-Reply-To: <20250730121209.303202-6-s.neeraj@samsung.com>
On 7/30/25 5:11 AM, Neeraj Kumar wrote:
> Added __pmem_region_label_update region label update routine to update
> region label.
>
> Also used guard(mutex)(&nd_mapping->lock) in place of mutex_lock() and
> mutex_unlock()
>
> Signed-off-by: Neeraj Kumar <s.neeraj@samsung.com>
Subject, s/updation/update/ ?
> ---
> drivers/nvdimm/label.c | 171 +++++++++++++++++++++++++++++---
> drivers/nvdimm/label.h | 2 +
> drivers/nvdimm/namespace_devs.c | 12 +++
> drivers/nvdimm/nd.h | 20 ++++
> include/linux/libnvdimm.h | 8 ++
> 5 files changed, 198 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/nvdimm/label.c b/drivers/nvdimm/label.c
> index 3f8a6bdb77c7..94f2d0ba7aca 100644
> --- a/drivers/nvdimm/label.c
> +++ b/drivers/nvdimm/label.c
> @@ -381,6 +381,16 @@ static void nsl_calculate_checksum(struct nvdimm_drvdata *ndd,
> nsl_set_checksum(ndd, nd_label, sum);
> }
>
> +static void rgl_calculate_checksum(struct nvdimm_drvdata *ndd,
region_label_checksum()? rgl/rg is just a bit jarring to read even though I get nvdimm already has nd and nsl etc.
> + struct cxl_region_label *rg_label)
Prefer just spell out region_label
> +{
> + u64 sum;
> +
> + rgl_set_checksum(rg_label, 0);
> + sum = nd_fletcher64(rg_label, sizeof_namespace_label(ndd), 1);
> + rgl_set_checksum(rg_label, sum);
> +}
> +
> static bool slot_valid(struct nvdimm_drvdata *ndd,
> struct nd_lsa_label *lsa_label, u32 slot)
> {
> @@ -960,7 +970,7 @@ static int __pmem_label_update(struct nd_region *nd_region,
> return rc;
>
> /* Garbage collect the previous label */
> - mutex_lock(&nd_mapping->lock);
> + guard(mutex)(&nd_mapping->lock);
> list_for_each_entry(label_ent, &nd_mapping->labels, list) {
> if (!label_ent->label)
> continue;
> @@ -972,20 +982,20 @@ static int __pmem_label_update(struct nd_region *nd_region,
> /* update index */
> rc = nd_label_write_index(ndd, ndd->ns_next,
> nd_inc_seq(__le32_to_cpu(nsindex->seq)), 0);
> - if (rc == 0) {
> - list_for_each_entry(label_ent, &nd_mapping->labels, list)
> - if (!label_ent->label) {
> - label_ent->label = lsa_label;
> - lsa_label = NULL;
> - break;
> - }
> - dev_WARN_ONCE(&nspm->nsio.common.dev, lsa_label,
> - "failed to track label: %d\n",
> - to_slot(ndd, lsa_label));
> - if (lsa_label)
> - rc = -ENXIO;
> - }
> - mutex_unlock(&nd_mapping->lock);
> + if (rc)
> + return rc;
> +
> + list_for_each_entry(label_ent, &nd_mapping->labels, list)
> + if (!label_ent->label) {
> + label_ent->label = lsa_label;
> + lsa_label = NULL;
> + break;
> + }
Would've preferred the original code to look like:
list_for_each_entry(label_ent, &nd_mapping->labels, list) {
if (label_ent->label)
continue;
label_ent->label = lsa_label;
lsa_label = NULL;
break;
}
But ah well....
> + dev_WARN_ONCE(&nspm->nsio.common.dev, lsa_label,> + "failed to track label: %d\n",
> + to_slot(ndd, lsa_label));
> + if (lsa_label)
> + rc = -ENXIO;
Just return here as Jonathan already mentioned. guard() helps with cleaning that up.
>
> return rc;
> }
> @@ -1127,6 +1137,137 @@ int nd_pmem_namespace_label_update(struct nd_region *nd_region,
> return 0;
> }
>
> +static int __pmem_region_label_update(struct nd_region *nd_region,
> + struct nd_mapping *nd_mapping, int pos, unsigned long flags)
> +{
> + struct nd_interleave_set *nd_set = nd_region->nd_set;
> + struct nvdimm_drvdata *ndd = to_ndd(nd_mapping);
> + struct nd_lsa_label *nd_label;
> + struct cxl_region_label *rg_label;
> + struct nd_namespace_index *nsindex;> + struct nd_label_ent *label_ent;
> + unsigned long *free;
> + u32 nslot, slot;
> + size_t offset;
> + int rc;
> + uuid_t tmp;
uuid instead of tmp would make the variable clearer to read
Also please arrange variable ordering in reverse xmas tree.
> +
> + if (!preamble_next(ndd, &nsindex, &free, &nslot))
> + return -ENXIO;
> +
> + /* allocate and write the label to the staging (next) index */
> + slot = nd_label_alloc_slot(ndd);
> + if (slot == UINT_MAX)
> + return -ENXIO;
> + dev_dbg(ndd->dev, "allocated: %d\n", slot);
> +
> + nd_label = to_label(ndd, slot);
> +
> + memset(nd_label, 0, sizeof_namespace_label(ndd));
> + rg_label = &nd_label->rg_label;
> +
> + /* Set Region Label Format identification UUID */
> + uuid_parse(CXL_REGION_UUID, &tmp);
> + export_uuid(nd_label->rg_label.type, &tmp);
> +
> + /* Set Current Region Label UUID */
> + export_uuid(nd_label->rg_label.uuid, &nd_set->uuid);
> +
> + rg_label->flags = __cpu_to_le32(flags);
> + rg_label->nlabel = __cpu_to_le16(nd_region->ndr_mappings);
> + rg_label->position = __cpu_to_le16(pos);
> + rg_label->dpa = __cpu_to_le64(nd_mapping->start);
> + rg_label->rawsize = __cpu_to_le64(nd_mapping->size);
> + rg_label->hpa = __cpu_to_le64(nd_set->res->start);
> + rg_label->slot = __cpu_to_le32(slot);
> + rg_label->ig = __cpu_to_le32(nd_set->interleave_granularity);
> + rg_label->align = __cpu_to_le16(0);
> +
> + /* Update fletcher64 Checksum */
> + rgl_calculate_checksum(ndd, rg_label);
> +
> + /* update label */
> + offset = nd_label_offset(ndd, nd_label);
> + rc = nvdimm_set_config_data(ndd, offset, nd_label,
> + sizeof_namespace_label(ndd));
> + if (rc < 0) {
> + nd_label_free_slot(ndd, slot);
> + return rc;
> + }
> +
> + /* Garbage collect the previous label */
> + guard(mutex)(&nd_mapping->lock);
> + list_for_each_entry(label_ent, &nd_mapping->labels, list) {
> + if (!label_ent->label)
> + continue;
> + if (rgl_uuid_equal(&label_ent->label->rg_label, &nd_set->uuid))
> + reap_victim(nd_mapping, label_ent);
> + }
> +
> + /* update index */
> + rc = nd_label_write_index(ndd, ndd->ns_next,
> + nd_inc_seq(__le32_to_cpu(nsindex->seq)), 0);
> + if (rc)
> + return rc;
> +
> + list_for_each_entry(label_ent, &nd_mapping->labels, list)
> + if (!label_ent->label) {
> + label_ent->label = nd_label;
> + nd_label = NULL;
> + break;
> + }
> + dev_WARN_ONCE(&nd_region->dev, nd_label,
> + "failed to track label: %d\n",
> + to_slot(ndd, nd_label));
> + if (nd_label)
> + rc = -ENXIO;
just return here
> +
> + return rc;
> +}
> +
> +int nd_pmem_region_label_update(struct nd_region *nd_region)
> +{
> + int i, rc;
> +
> + for (i = 0; i < nd_region->ndr_mappings; i++) {
> + struct nd_mapping *nd_mapping = &nd_region->mapping[i];
> + struct nvdimm_drvdata *ndd = to_ndd(nd_mapping);
> +
> + /* No need to update region label for non cxl format */
> + if (!ndd->cxl)
> + continue;
Would there be a mix of different nd mappings? I wonder if you can just 'return 0' if you find ndd->cxl on the first one and just skip everything.
> +
> + /* Init labels to include region label */
> + rc = init_labels(nd_mapping, 1);
> +
> + if (rc < 0)
> + return rc;
> +
> + rc = __pmem_region_label_update(nd_region, nd_mapping, i,
> + NSLABEL_FLAG_UPDATING);
> +
> + if (rc)
> + return rc;
> + }
> +
> + /* Clear the UPDATING flag per UEFI 2.7 expectations */
> + for (i = 0; i < nd_region->ndr_mappings; i++) {
> + struct nd_mapping *nd_mapping = &nd_region->mapping[i];
> + struct nvdimm_drvdata *ndd = to_ndd(nd_mapping);
> +
> + /* No need to update region label for non cxl format */
> + if (!ndd->cxl)
> + continue;
> +> + rc = __pmem_region_label_update(nd_region, nd_mapping, i, 0);
> +
> + if (rc)
> + return rc;
> + }
> +
> + return 0;
> +}
> +
> int __init nd_label_init(void)
> {
> WARN_ON(guid_parse(NVDIMM_BTT_GUID, &nvdimm_btt_guid));
> diff --git a/drivers/nvdimm/label.h b/drivers/nvdimm/label.h
> index 4883b3a1320f..0f428695017d 100644
> --- a/drivers/nvdimm/label.h
> +++ b/drivers/nvdimm/label.h
> @@ -190,6 +190,7 @@ struct nd_namespace_label {
> struct nd_lsa_label {
> union {
> struct nd_namespace_label ns_label;
> + struct cxl_region_label rg_label;
> };
> };
>
> @@ -233,4 +234,5 @@ struct nd_region;
> struct nd_namespace_pmem;
> int nd_pmem_namespace_label_update(struct nd_region *nd_region,
> struct nd_namespace_pmem *nspm, resource_size_t size);
> +int nd_pmem_region_label_update(struct nd_region *nd_region);
> #endif /* __LABEL_H__ */
> diff --git a/drivers/nvdimm/namespace_devs.c b/drivers/nvdimm/namespace_devs.c
> index 5b73119dc8fd..02ae8162566c 100644
> --- a/drivers/nvdimm/namespace_devs.c
> +++ b/drivers/nvdimm/namespace_devs.c
> @@ -232,6 +232,18 @@ static ssize_t __alt_name_store(struct device *dev, const char *buf,
> return rc;
> }
>
> +int nd_region_label_update(struct nd_region *nd_region)
> +{
> + int rc;
> +
> + nvdimm_bus_lock(&nd_region->dev);
> + rc = nd_pmem_region_label_update(nd_region);
> + nvdimm_bus_unlock(&nd_region->dev);
> +
> + return rc;
> +}
> +EXPORT_SYMBOL_GPL(nd_region_label_update);
> +
> static int nd_namespace_label_update(struct nd_region *nd_region,
> struct device *dev)
> {
> diff --git a/drivers/nvdimm/nd.h b/drivers/nvdimm/nd.h
> index 651847f1bbf9..15d94e3937f0 100644
> --- a/drivers/nvdimm/nd.h
> +++ b/drivers/nvdimm/nd.h
> @@ -322,6 +322,26 @@ static inline void nsl_set_region_uuid(struct nvdimm_drvdata *ndd,
> export_uuid(ns_label->cxl.region_uuid, uuid);
> }
>
> +static inline bool rgl_uuid_equal(struct cxl_region_label *rg_label,
> + const uuid_t *uuid)
region_label_uuid_equal() and region_label
> +{
> + uuid_t tmp;
tmp_uuid
> +
> + import_uuid(&tmp, rg_label->uuid);
> + return uuid_equal(&tmp, uuid);
> +}
> +
> +static inline u64 rgl_get_checksum(struct cxl_region_label *rg_label)
region_label_get_checksum()
> +{
> + return __le64_to_cpu(rg_label->checksum);
> +}
> +
> +static inline void rgl_set_checksum(struct cxl_region_label *rg_label,
region_label_set_checksum()
> + u64 checksum)
> +{
> + rg_label->checksum = __cpu_to_le64(checksum);
> +}
> +
> bool nsl_validate_type_guid(struct nvdimm_drvdata *ndd,
> struct nd_namespace_label *nd_label, guid_t *guid);
> enum nvdimm_claim_class nsl_get_claim_class(struct nvdimm_drvdata *ndd,
> diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h
> index 0a55900842c8..b06bd45373f4 100644
> --- a/include/linux/libnvdimm.h
> +++ b/include/linux/libnvdimm.h
> @@ -115,6 +115,13 @@ struct nd_interleave_set {
> u64 altcookie;
>
> guid_t type_guid;
> +
> + /* v2.1 region label info */
> + uuid_t uuid;
> + int interleave_ways;
> + int interleave_granularity;
> + struct resource *res;
> + int nr_targets;
> };
>
> struct nd_mapping_desc {
> @@ -302,6 +309,7 @@ int nvdimm_has_flush(struct nd_region *nd_region);
> int nvdimm_has_cache(struct nd_region *nd_region);
> int nvdimm_in_overwrite(struct nvdimm *nvdimm);
> bool is_nvdimm_sync(struct nd_region *nd_region);
> +int nd_region_label_update(struct nd_region *nd_region);
>
> static inline int nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd, void *buf,
> unsigned int buf_len, int *cmd_rc)
next prev parent reply other threads:[~2025-08-15 21:55 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250730121221epcas5p3ffb9e643af6b8ae07cfccf0bdee90e37@epcas5p3.samsung.com>
2025-07-30 12:11 ` [PATCH V2 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
[not found] ` <CGME20250730121223epcas5p1386bdf99a0af820dd4411fbdbd413cd5@epcas5p1.samsung.com>
2025-07-30 12:11 ` [PATCH V2 01/20] nvdimm/label: Introduce NDD_CXL_LABEL flag to set cxl label format Neeraj Kumar
2025-08-13 13:12 ` Jonathan Cameron
2025-08-15 18:06 ` Dave Jiang
2025-09-04 13:24 ` Neeraj Kumar
2025-09-04 13:20 ` Neeraj Kumar
[not found] ` <CGME20250730121224epcas5p3c3a6563ce186d2fdb9c3ff5f66e37f3e@epcas5p3.samsung.com>
2025-07-30 12:11 ` [PATCH V2 02/20] nvdimm/label: Prep patch to accommodate cxl lsa 2.1 support Neeraj Kumar
2025-08-13 13:23 ` Jonathan Cameron
2025-09-04 13:27 ` Neeraj Kumar
2025-08-15 22:02 ` Dave Jiang
2025-09-04 13:31 ` Neeraj Kumar
2025-08-18 21:48 ` Dave Jiang
2025-09-04 13:33 ` Neeraj Kumar
2025-08-19 15:38 ` Ira Weiny
2025-09-04 13:42 ` Neeraj Kumar
[not found] ` <CGME20250730121225epcas5p2742d108bd0c52c8d7d46b655892c5c19@epcas5p2.samsung.com>
2025-07-30 12:11 ` [PATCH V2 03/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1 Neeraj Kumar
2025-07-31 13:12 ` kernel test robot
2025-08-13 13:27 ` Jonathan Cameron
2025-09-04 13:40 ` Neeraj Kumar
2025-08-19 15:57 ` Ira Weiny
2025-09-04 13:51 ` Neeraj Kumar
2025-08-19 19:36 ` Ira Weiny
2025-09-05 5:34 ` Neeraj Kumar
[not found] ` <CGME20250730121227epcas5p4675fdb3130de49cd99351c5efd09e29e@epcas5p4.samsung.com>
2025-07-30 12:11 ` [PATCH V2 04/20] nvdimm/label: CXL labels skip the need for 'interleave-set cookie' Neeraj Kumar
2025-08-13 13:44 ` Jonathan Cameron
2025-09-04 13:54 ` Neeraj Kumar
2025-08-15 21:02 ` Dave Jiang
2025-09-04 14:01 ` Neeraj Kumar
2025-08-19 16:04 ` Ira Weiny
2025-09-04 14:02 ` Neeraj Kumar
[not found] ` <CGME20250730121228epcas5p411e5cc6d29fb9417178dbd07a1d8f02d@epcas5p4.samsung.com>
2025-07-30 12:11 ` [PATCH V2 05/20] nvdimm/region_label: Add region label updation routine Neeraj Kumar
2025-07-31 15:07 ` kernel test robot
2025-08-13 14:48 ` Jonathan Cameron
2025-09-04 14:06 ` Neeraj Kumar
2025-08-15 21:55 ` Dave Jiang [this message]
2025-09-04 14:12 ` Neeraj Kumar
2025-09-10 14:03 ` Jonathan Cameron
2025-08-15 23:12 ` Dave Jiang
2025-09-04 14:13 ` Neeraj Kumar
2025-08-19 18:16 ` Ira Weiny
2025-09-04 14:18 ` Neeraj Kumar
[not found] ` <CGME20250730121230epcas5p11650f090de55d0a2db541ee32e9a6fee@epcas5p1.samsung.com>
2025-07-30 12:11 ` [PATCH V2 06/20] nvdimm/region_label: Add region label deletion routine Neeraj Kumar
2025-08-13 14:53 ` Jonathan Cameron
2025-09-04 14:20 ` Neeraj Kumar
2025-08-15 22:22 ` Dave Jiang
2025-09-04 14:23 ` Neeraj Kumar
[not found] ` <CGME20250730121231epcas5p2c12cb2b4914279d1f1c93e56a32c3908@epcas5p2.samsung.com>
2025-07-30 12:11 ` [PATCH V2 07/20] nvdimm/namespace_label: Update namespace init_labels and its region_uuid Neeraj Kumar
2025-08-13 14:58 ` Jonathan Cameron
2025-09-04 14:24 ` Neeraj Kumar
2025-08-19 18:56 ` Ira Weiny
2025-09-04 14:28 ` Neeraj Kumar
2025-09-05 20:08 ` Ira Weiny
2025-09-08 5:36 ` Neeraj Kumar
[not found] ` <CGME20250730121232epcas5p4cd632fe09d1bc51499d9e3ac3c2633b3@epcas5p4.samsung.com>
2025-07-30 12:11 ` [PATCH V2 08/20] nvdimm/label: Include region label in slot validation Neeraj Kumar
2025-08-13 15:07 ` Jonathan Cameron
2025-09-04 14:30 ` Neeraj Kumar
[not found] ` <CGME20250730121234epcas5p2605fbec7bc95f6096550792844b8f8ee@epcas5p2.samsung.com>
2025-07-30 12:11 ` [PATCH V2 09/20] nvdimm/namespace_label: Skip region label during ns label DPA reservation Neeraj Kumar
2025-08-13 15:09 ` Jonathan Cameron
2025-09-04 14:31 ` Neeraj Kumar
[not found] ` <CGME20250730121235epcas5p4494147524e77e99bc16d9b510e8971a4@epcas5p4.samsung.com>
2025-07-30 12:11 ` [PATCH V2 10/20] nvdimm/region_label: Preserve cxl region information from region label Neeraj Kumar
2025-08-13 15:11 ` Jonathan Cameron
2025-09-04 14:33 ` Neeraj Kumar
[not found] ` <CGME20250730121236epcas5p4b8939ed1bfff468c965a9dbd6bc261b6@epcas5p4.samsung.com>
2025-07-30 12:12 ` [PATCH V2 11/20] nvdimm/region_label: Export routine to fetch region information Neeraj Kumar
2025-08-13 15:13 ` Jonathan Cameron
[not found] ` <CGME20250730121238epcas5p212dcce5cc5713173913ee154d5098a2c@epcas5p2.samsung.com>
2025-07-30 12:12 ` [PATCH V2 12/20] nvdimm/namespace_label: Skip region label during namespace creation Neeraj Kumar
2025-08-13 15:55 ` Jonathan Cameron
2025-09-04 14:34 ` Neeraj Kumar
[not found] ` <CGME20250730121239epcas5p37956b2999f61e17e8dbfbde7972cef35@epcas5p3.samsung.com>
2025-07-30 12:12 ` [PATCH V2 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar
2025-08-20 16:41 ` Dave Jiang
2025-09-04 14:39 ` Neeraj Kumar
[not found] ` <CGME20250730121241epcas5p3e5708a89d764d1de9322fd759f921de0@epcas5p3.samsung.com>
2025-07-30 12:12 ` [PATCH V2 14/20] cxl/region: Add devm_cxl_pmem_add_region() for pmem region creation Neeraj Kumar
2025-08-20 0:30 ` Dave Jiang
2025-09-04 14:55 ` Neeraj Kumar
[not found] ` <CGME20250730121242epcas5p4bdfc11e82e28d525364262fb2b6d8feb@epcas5p4.samsung.com>
2025-07-30 12:12 ` [PATCH V2 15/20] cxl: Add a routine to find cxl root decoder on cxl bus using cxl port Neeraj Kumar
[not found] ` <CGME20250730121243epcas5p4c40126a3cf5c8019b36eb8287c3ec2c8@epcas5p4.samsung.com>
2025-07-30 12:12 ` [PATCH V2 16/20] cxl/mem: Preserve cxl root decoder during mem probe Neeraj Kumar
[not found] ` <CGME20250730121245epcas5p247b6675350f4f7e70e9b3c8465340e84@epcas5p2.samsung.com>
2025-07-30 12:12 ` [PATCH V2 17/20] cxl/pmem: Preserve region information into nd_set Neeraj Kumar
[not found] ` <CGME20250730121246epcas5p48a2fd8e653f05a0282cbffc1f702f26f@epcas5p4.samsung.com>
2025-07-30 12:12 ` [PATCH V2 18/20] cxl/pmem: Add support of cxl lsa 2.1 support in cxl pmem Neeraj Kumar
2025-07-31 1:36 ` kernel test robot
[not found] ` <CGME20250730121247epcas5p425b79da65bcb003917cbf02fc047a7db@epcas5p4.samsung.com>
2025-07-30 12:12 ` [PATCH V2 19/20] cxl/pmem_region: Prep patch to accommodate pmem_region attributes Neeraj Kumar
2025-07-31 1:57 ` kernel test robot
2025-07-31 2:17 ` kernel test robot
[not found] ` <CGME20250730121249epcas5p249c2e3fec3464cfea3a1c84bc285cd49@epcas5p2.samsung.com>
2025-07-30 12:12 ` [PATCH V2 20/20] cxl/pmem_region: Add sysfs attribute cxl region label updation/deletion Neeraj Kumar
2025-07-31 10:36 ` kernel test robot
2025-08-07 9:02 ` [PATCH V2 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
2025-08-12 21:46 ` Dave Jiang
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