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Wed, 13 Dec 2023 21:32:37 GMT Received: from [10.71.109.77] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 13:32:36 -0800 Message-ID: <534d7029-c772-cf15-0eb7-219471e258a5@quicinc.com> Date: Wed, 13 Dec 2023 13:32:35 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v4 2/2] drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr() Content-Language: en-US To: Jessica Zhang , Rob Clark , Dmitry Baryshkov , "Sean Paul" , Marijn Suijten , "David Airlie" , Daniel Vetter CC: , , , References: <20231213-encoder-fixup-v4-0-6da6cd1bf118@quicinc.com> <20231213-encoder-fixup-v4-2-6da6cd1bf118@quicinc.com> From: Abhinav Kumar In-Reply-To: <20231213-encoder-fixup-v4-2-6da6cd1bf118@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: UwBQ69UB3RYNmwg7bhC8NvKDKxNux52U X-Proofpoint-GUID: UwBQ69UB3RYNmwg7bhC8NvKDKxNux52U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 clxscore=1015 mlxlogscore=873 priorityscore=1501 mlxscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312130151 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/13/2023 1:30 PM, Jessica Zhang wrote: > Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they > are always set to the same values. > > In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as > frame_count is always set to the same value. > > Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util") > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Jessica Zhang > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++--- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++--- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 19 +++++-------------- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 9 +++------ > 8 files changed, 22 insertions(+), 33 deletions(-) > Reviewed-by: Abhinav Kumar