From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 271DDCDB465 for ; Mon, 16 Oct 2023 19:46:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233351AbjJPTqB (ORCPT ); Mon, 16 Oct 2023 15:46:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232988AbjJPTpz (ORCPT ); Mon, 16 Oct 2023 15:45:55 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC0B983 for ; Mon, 16 Oct 2023 12:45:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1697485504; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=04LjIwtYGGBaqDl5gBQzyzheSzqfZG47EyQuGN124eA=; b=G3dFPuxaLztQO/KreLuAIodnV56wD1DZOre7ryHEW1XdlBJ3Cgfa3lhpxB9B0l8Wjdz/gM ezpzcvZQpacsCSv1A7qXuNZDHiH/mIk6VMJ1oyAY05l3QI8iGkusmUuTXenaBHBsWE7Vx3 ty7z2fRBRsDCg3f7lAH3yexbel/UFTs= Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-677--fECsdZeMGuJDGS6JMs_dg-1; Mon, 16 Oct 2023 15:45:03 -0400 X-MC-Unique: -fECsdZeMGuJDGS6JMs_dg-1 Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-66d062708b0so59924026d6.1 for ; Mon, 16 Oct 2023 12:45:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697485503; x=1698090303; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=04LjIwtYGGBaqDl5gBQzyzheSzqfZG47EyQuGN124eA=; b=SdoIz2fpJhYLFbHQqpQ4L+XOllBHQWaqYWZkskxm8CUbQ0v6llRLCJxz5tQo0mnEH8 bShI59bvkFZc6smZBbwm8DRPDQ1pSnL18SOkOwOIyT2TwMBWRWsH6yh9rBa+fXFpJH7a P6m8VpKohzzP93yMqxUFIxO1LSWr8Go4d3yqDxhC8zeVjI/77AjylO+1DMdrjw+vNwr9 uSdwbpeDm9zo0M/7n1ekqpjuqkJYPoU+wiiM25QUv5Eqxa2fkuycxrTn4yFEcwzWfW3H XyAEsx8XIAtU5MR8q2MAJqHD9qDJeLB5YsL+ph7hNK1ZSaKV3s+ASgZySXSi3V+loIUQ /uEw== X-Gm-Message-State: AOJu0YxkyN/B8/01EJ0h65MOkxmq/nAUuf5t9MRnZhcaLyRIlYxDpH+R vKLX1hw1r1Eq/rA+pcKJhiGWIBirlcU2Q0CAoi+1nhPzP8roD9JWBv0NgqZoqggr/ggNd8YOwL1 eu4hXZIiFRLZ43Rey2zihYfR4 X-Received: by 2002:a05:6214:c49:b0:66d:114c:bdd5 with SMTP id r9-20020a0562140c4900b0066d114cbdd5mr477442qvj.39.1697485503130; Mon, 16 Oct 2023 12:45:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEv0GXtH++psTY27fTmUPNDZligDmsLJ+tncVL81/Bq0tJgMaEP5J9Ly9VcQTdNnf7OsYUmKQ== X-Received: by 2002:a05:6214:c49:b0:66d:114c:bdd5 with SMTP id r9-20020a0562140c4900b0066d114cbdd5mr477421qvj.39.1697485502861; Mon, 16 Oct 2023 12:45:02 -0700 (PDT) Received: from [192.168.43.95] ([37.170.191.221]) by smtp.gmail.com with ESMTPSA id e11-20020a05620a12cb00b0076db1caab16sm3256901qkl.22.2023.10.16.12.44.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Oct 2023 12:45:02 -0700 (PDT) Message-ID: <53546f35-f2cc-4c75-171c-26719550f7df@redhat.com> Date: Mon, 16 Oct 2023 21:44:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v7 03/12] KVM: arm64: PMU: Clear PM{C,I}NTEN{SET,CLR} and PMOVS{SET,CLR} on vCPU reset Content-Language: en-US To: Raghavendra Rao Ananta , Oliver Upton , Marc Zyngier Cc: Alexandru Elisei , James Morse , Suzuki K Poulose , Paolo Bonzini , Zenghui Yu , Shaoqin Huang , Jing Zhang , Reiji Watanabe , Colton Lewis , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org References: <20231009230858.3444834-1-rananta@google.com> <20231009230858.3444834-4-rananta@google.com> From: Eric Auger In-Reply-To: <20231009230858.3444834-4-rananta@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Raghavendra, On 10/10/23 01:08, Raghavendra Rao Ananta wrote: > From: Reiji Watanabe > > On vCPU reset, PMCNTEN{SET,CLR}_EL0, PMINTEN{SET,CLR}_EL1, and > PMOVS{SET,CLR}_EL1 for a vCPU are reset by reset_pmu_reg(). PMOVS{SET,CLR}_EL0? > This function clears RAZ bits of those registers corresponding > to unimplemented event counters on the vCPU, and sets bits > corresponding to implemented event counters to a predefined > pseudo UNKNOWN value (some bits are set to 1). > > The function identifies (un)implemented event counters on the > vCPU based on the PMCR_EL0.N value on the host. Using the host > value for this would be problematic when KVM supports letting > userspace set PMCR_EL0.N to a value different from the host value > (some of the RAZ bits of those registers could end up being set to 1). > > Fix this by clearing the registers so that it can ensure > that all the RAZ bits are cleared even when the PMCR_EL0.N value > for the vCPU is different from the host value. Use reset_val() to > do this instead of fixing reset_pmu_reg(), and remove > reset_pmu_reg(), as it is no longer used. do you intend to restore the 'unknown' behavior at some point? Thanks Eric > > Signed-off-by: Reiji Watanabe > Signed-off-by: Raghavendra Rao Ananta > --- > arch/arm64/kvm/sys_regs.c | 21 +-------------------- > 1 file changed, 1 insertion(+), 20 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 818a52e257ed..3dbb7d276b0e 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -717,25 +717,6 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, > return REG_HIDDEN; > } > > -static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > -{ > - u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); > - > - /* No PMU available, any PMU reg may UNDEF... */ > - if (!kvm_arm_support_pmu_v3()) > - return 0; > - > - n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; > - n &= ARMV8_PMU_PMCR_N_MASK; > - if (n) > - mask |= GENMASK(n - 1, 0); > - > - reset_unknown(vcpu, r); > - __vcpu_sys_reg(vcpu, r->reg) &= mask; > - > - return __vcpu_sys_reg(vcpu, r->reg); > -} > - > static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > { > reset_unknown(vcpu, r); > @@ -1115,7 +1096,7 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } > > #define PMU_SYS_REG(name) \ > - SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ > + SYS_DESC(SYS_##name), .reset = reset_val, \ > .visibility = pmu_visibility > > /* Macro to expand the PMEVCNTRn_EL0 register */