Re: [kvm-unit-tests patch v6 13/18] x86: pmu: Improve instruction and branches events verification

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

On 2/15/2025 5:08 AM, Sean Christopherson wrote:
> On Sat, Sep 14, 2024, Dapeng Mi wrote:
>> If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are moved in
>> __precise_count_loop(). Thus, instructions and branches events can be
>> verified against a precise count instead of a rough range.
>>
>> BTW, some intermittent failures on AMD processors using PerfMonV2 is
>> seen due to variance in counts. This probably has to do with the way
>> instructions leading to a VM-Entry or VM-Exit are accounted when
>> counting retired instructions and branches.
> AMD counts VMRUN as a branch in guest context.

Good to know. Thanks.


>
>> +	 * We see some intermittent failures on AMD processors using PerfMonV2
>> +	 * due to variance in counts. This probably has to do with the way
>> +	 * instructions leading to a VM-Entry or VM-Exit are accounted when
>> +	 * counting retired instructions and branches. Thus only enable the
>> +	 * precise validation for Intel processors.
>> +	 */
>> +	if (pmu.is_intel && this_cpu_has_perf_global_ctrl()) {
>> +		/* instructions event */
> These comments are useless.

Sure.


>
>> +		gp_events[instruction_idx].min = LOOP_INSTRNS;
>> +		gp_events[instruction_idx].max = LOOP_INSTRNS;
>> +		/* branches event */
>> +		gp_events[branch_idx].min = LOOP_BRANCHES;
>> +		gp_events[branch_idx].max = LOOP_BRANCHES;
>> +	}
>> +}