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Wed, 21 Oct 2026 13:04:59 -0700 (PDT) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93f56d98978sm336971485a.10.2026.10.21.13.04.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 13:04:58 -0700 (PDT) Message-ID: <5388e60d-6418-4b84-8a88-5e647248025d@gmail.com> Date: Wed, 21 Oct 2026 13:04:55 -0700 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] MIPS: Cobalt: Include legacy IDE ports in the PCI I/O window To: "Maciej W. Rozycki" Cc: linux-mips@vger.kernel.org, ilpo.jarvinen@linux.intel.com, Thomas Bogendoerfer , Bjorn Helgaas , open list References: <20261015203107.545047-1-f.fainelli@gmail.com> Content-Language: en-US, fr-FR From: Florian Fainelli In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/20/26 10:13, Maciej W. Rozycki wrote: > On Thu, 15 Oct 2026, Florian Fainelli wrote: > >> The Cobalt PCI I/O window starts at 0x1000, excluding the VIA IDE >> controller's fixed compatibility-mode ports at 0x170, 0x1f0, 0x376 and >> 0x3f6. These resources cannot be claimed under the host bridge window. >> >> Since pcibios_enable_device() was converted to pci_enable_resources(), >> the unclaimed IDE resources cause device enable to fail with -EINVAL: >> >> pata_via 0000:00:09.1: BAR 0 [io 0x01f0-0x01f7]: not claimed; can't enable device >> pata_via 0000:00:09.1: probe with driver pata_via failed with error -22 >> >> Lower the PCI I/O window start to 0x100 so the fixed IDE resources can >> be claimed. Keep the reserved ISA resources below 0x100 outside the PCI >> window. > > Why not go with 0 (unless that's not what the system controller supports > as the bottom of the PCI I/O space), and just set PCIBIOS_MIN_IO correctly > as several platforms do instead? Is there a southbridge in your system? 0 does not work and gives me: [ 0.205993] Skipping PCI bus scan due to resource conflict There is no south bridge AFAICT, the CPU connection to the GT-64111. -- Florian