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From: Andy Lutomirski <luto@amacapital.net>
To: Qiaowei Ren <qiaowei.ren@intel.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>,
	Dave Hansen <dave.hansen@intel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 04/10] x86, mpx: hook #BR exception handler to allocate bound tables
Date: Mon, 23 Jun 2014 12:54:46 -0700	[thread overview]
Message-ID: <53A88606.2050108@mit.edu> (raw)
In-Reply-To: <1403084656-27284-5-git-send-email-qiaowei.ren@intel.com>

On 06/18/2014 02:44 AM, Qiaowei Ren wrote:
> This patch handles a #BR exception for non-existent tables by
> carving the space out of the normal processes address space
> (essentially calling mmap() from inside the kernel) and then
> pointing the bounds-directory over to it.
> 
> The tables need to be accessed and controlled by userspace
> because the compiler generates instructions for MPX-enabled
> code which frequently store and retrieve entries from the bounds
> tables. Any direct kernel involvement (like a syscall) to access
> the tables would destroy performance since these are so frequent.
> 
> The tables are carved out of userspace because we have no better
> spot to put them. For each pointer which is being tracked by MPX,
> the bounds tables contain 4 longs worth of data, and the tables
> are indexed virtually. If we were to preallocate the tables, we
> would theoretically need to allocate 4x the virtual space that
> we have available for userspace somewhere else. We don't have
> that room in the kernel address space.
> 
> Signed-off-by: Qiaowei Ren <qiaowei.ren@intel.com>
> ---
>  arch/x86/include/asm/mpx.h |   20 ++++++++++++++
>  arch/x86/kernel/Makefile   |    1 +
>  arch/x86/kernel/mpx.c      |   63 ++++++++++++++++++++++++++++++++++++++++++++
>  arch/x86/kernel/traps.c    |   56 ++++++++++++++++++++++++++++++++++++++-
>  4 files changed, 139 insertions(+), 1 deletions(-)
>  create mode 100644 arch/x86/kernel/mpx.c
> 
> diff --git a/arch/x86/include/asm/mpx.h b/arch/x86/include/asm/mpx.h
> index 5725ac4..b7598ac 100644
> --- a/arch/x86/include/asm/mpx.h
> +++ b/arch/x86/include/asm/mpx.h
> @@ -18,6 +18,8 @@
>  #define MPX_BT_ENTRY_SHIFT	5
>  #define MPX_IGN_BITS		3
>  
> +#define MPX_BD_ENTRY_TAIL	3
> +
>  #else
>  
>  #define MPX_BD_ENTRY_OFFSET	20
> @@ -26,13 +28,31 @@
>  #define MPX_BT_ENTRY_SHIFT	4
>  #define MPX_IGN_BITS		2
>  
> +#define MPX_BD_ENTRY_TAIL	2
> +
>  #endif
>  
> +#define MPX_BNDSTA_TAIL		2
> +#define MPX_BNDCFG_TAIL		12
> +#define MPX_BNDSTA_ADDR_MASK	(~((1UL<<MPX_BNDSTA_TAIL)-1))
> +#define MPX_BNDCFG_ADDR_MASK	(~((1UL<<MPX_BNDCFG_TAIL)-1))
> +#define MPX_BT_ADDR_MASK	(~((1UL<<MPX_BD_ENTRY_TAIL)-1))
> +
>  #define MPX_BD_SIZE_BYTES (1UL<<(MPX_BD_ENTRY_OFFSET+MPX_BD_ENTRY_SHIFT))
>  #define MPX_BT_SIZE_BYTES (1UL<<(MPX_BT_ENTRY_OFFSET+MPX_BT_ENTRY_SHIFT))
>  
>  #define MPX_BNDSTA_ERROR_CODE	0x3
> +#define MPX_BD_ENTRY_VALID_FLAG	0x1
>  
>  unsigned long mpx_mmap(unsigned long len);
>  
> +#ifdef CONFIG_X86_INTEL_MPX
> +int do_mpx_bt_fault(struct xsave_struct *xsave_buf);
> +#else
> +static inline int do_mpx_bt_fault(struct xsave_struct *xsave_buf)
> +{
> +	return -EINVAL;
> +}
> +#endif /* CONFIG_X86_INTEL_MPX */
> +
>  #endif /* _ASM_X86_MPX_H */
> diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
> index f4d9600..3e81aed 100644
> --- a/arch/x86/kernel/Makefile
> +++ b/arch/x86/kernel/Makefile
> @@ -41,6 +41,7 @@ obj-$(CONFIG_PREEMPT)	+= preempt.o
>  
>  obj-y				+= process.o
>  obj-y				+= i387.o xsave.o
> +obj-$(CONFIG_X86_INTEL_MPX)	+= mpx.o
>  obj-y				+= ptrace.o
>  obj-$(CONFIG_X86_32)		+= tls.o
>  obj-$(CONFIG_IA32_EMULATION)	+= tls.o
> diff --git a/arch/x86/kernel/mpx.c b/arch/x86/kernel/mpx.c
> new file mode 100644
> index 0000000..4230c7b
> --- /dev/null
> +++ b/arch/x86/kernel/mpx.c
> @@ -0,0 +1,63 @@
> +#include <linux/kernel.h>
> +#include <linux/syscalls.h>
> +#include <asm/mpx.h>
> +
> +static int allocate_bt(long __user *bd_entry)
> +{
> +	unsigned long bt_addr, old_val = 0;
> +	int ret = 0;
> +
> +	bt_addr = mpx_mmap(MPX_BT_SIZE_BYTES);
> +	if (IS_ERR((void *)bt_addr)) {
> +		pr_err("Bounds table allocation failed at entry addr %p\n",
> +				bd_entry);
> +		return bt_addr;
> +	}
> +	bt_addr = (bt_addr & MPX_BT_ADDR_MASK) | MPX_BD_ENTRY_VALID_FLAG;
> +
> +	ret = user_atomic_cmpxchg_inatomic(&old_val, bd_entry, 0, bt_addr);
> +	if (ret)
> +		goto out;
> +
> +	/*
> +	 * there is a existing bounds table pointed at this bounds
> +	 * directory entry, and so we need to free the bounds table
> +	 * allocated just now.
> +	 */
> +	if (old_val)
> +		goto out;
> +
> +	pr_debug("Allocate bounds table %lx at entry %p\n",
> +			bt_addr, bd_entry);
> +	return 0;
> +
> +out:
> +	vm_munmap(bt_addr & MPX_BT_ADDR_MASK, MPX_BT_SIZE_BYTES);
> +	return ret;
> +}
> +
> +/*
> + * When a BNDSTX instruction attempts to save bounds to a BD entry
> + * with the lack of the valid bit being set, a #BR is generated.
> + * This is an indication that no BT exists for this entry. In this
> + * case the fault handler will allocate a new BT.
> + *
> + * With 32-bit mode, the size of BD is 4MB, and the size of each
> + * bound table is 16KB. With 64-bit mode, the size of BD is 2GB,
> + * and the size of each bound table is 4MB.
> + */
> +int do_mpx_bt_fault(struct xsave_struct *xsave_buf)
> +{
> +	unsigned long status;
> +	unsigned long bd_entry, bd_base;
> +
> +	bd_base = xsave_buf->bndcsr.cfg_reg_u & MPX_BNDCFG_ADDR_MASK;
> +	status = xsave_buf->bndcsr.status_reg;
> +
> +	bd_entry = status & MPX_BNDSTA_ADDR_MASK;
> +	if ((bd_entry < bd_base) ||
> +		(bd_entry >= bd_base + MPX_BD_SIZE_BYTES))
> +		return -EINVAL;
> +
> +	return allocate_bt((long __user *)bd_entry);
> +}
> diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
> index f73b5d4..35b9b29 100644
> --- a/arch/x86/kernel/traps.c
> +++ b/arch/x86/kernel/traps.c
> @@ -59,6 +59,7 @@
>  #include <asm/fixmap.h>
>  #include <asm/mach_traps.h>
>  #include <asm/alternative.h>
> +#include <asm/mpx.h>
>  
>  #ifdef CONFIG_X86_64
>  #include <asm/x86_init.h>
> @@ -213,7 +214,6 @@ dotraplinkage void do_##name(struct pt_regs *regs, long error_code)	\
>  
>  DO_ERROR_INFO(X86_TRAP_DE,     SIGFPE,  "divide error",			divide_error,		     FPE_INTDIV, regs->ip )
>  DO_ERROR     (X86_TRAP_OF,     SIGSEGV, "overflow",			overflow					  )
> -DO_ERROR     (X86_TRAP_BR,     SIGSEGV, "bounds",			bounds						  )
>  DO_ERROR_INFO(X86_TRAP_UD,     SIGILL,  "invalid opcode",		invalid_op,		     ILL_ILLOPN, regs->ip )
>  DO_ERROR     (X86_TRAP_OLD_MF, SIGFPE,  "coprocessor segment overrun",	coprocessor_segment_overrun			  )
>  DO_ERROR     (X86_TRAP_TS,     SIGSEGV, "invalid TSS",			invalid_TSS					  )
> @@ -263,6 +263,60 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
>  }
>  #endif
>  
> +dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
> +{
> +	enum ctx_state prev_state;
> +	unsigned long status;
> +	struct xsave_struct *xsave_buf;
> +	struct task_struct *tsk = current;
> +
> +	prev_state = exception_enter();
> +	if (notify_die(DIE_TRAP, "bounds", regs, error_code,
> +			X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
> +		goto exit;
> +	conditional_sti(regs);
> +
> +	if (!user_mode(regs))
> +		die("bounds", regs, error_code);

Does this need to be user_mode_vm?

> +
> +	if (!cpu_has_mpx) {
> +		/* The exception is not from Intel MPX */
> +		do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL);
> +		goto exit;
> +	}
> +
> +	fpu_xsave(&tsk->thread.fpu);
> +	xsave_buf = &(tsk->thread.fpu.state->xsave);
> +	status = xsave_buf->bndcsr.status_reg;
> +
> +	/*
> +	 * The error code field of the BNDSTATUS register communicates status
> +	 * information of a bound range exception #BR or operation involving
> +	 * bound directory.
> +	 */
> +	switch (status & MPX_BNDSTA_ERROR_CODE) {
> +	case 2:
> +		/*
> +		 * Bound directory has invalid entry.
> +		 * No signal will be sent to the user space.

This comment is a lie.

> +		 */
> +		if (do_mpx_bt_fault(xsave_buf))
> +			force_sig(SIGBUS, tsk);

Would it make sense to assign and use a new si_code value here?

--Andy

  reply	other threads:[~2014-06-23 19:54 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-18  9:44 [PATCH v6 00/10] Intel MPX support Qiaowei Ren
2014-06-18  9:44 ` [PATCH v6 01/10] x86, mpx: introduce VM_MPX to indicate that a VMA is MPX specific Qiaowei Ren
2014-06-18  9:44 ` [PATCH v6 02/10] x86, mpx: add MPX specific mmap interface Qiaowei Ren
2014-06-23 19:49   ` Andy Lutomirski
2014-06-23 20:03     ` Dave Hansen
2014-06-23 20:06       ` Andy Lutomirski
2014-06-23 20:28         ` Dave Hansen
2014-06-23 21:04           ` Andy Lutomirski
2014-06-24  5:53             ` Ren, Qiaowei
2014-06-24 23:55               ` Andy Lutomirski
2014-06-25  1:40                 ` Ren, Qiaowei
2014-06-25 21:04                   ` Andy Lutomirski
2014-06-25 21:05                     ` Andy Lutomirski
2014-06-25 21:45                       ` Dave Hansen
2014-06-26 22:19                         ` Andy Lutomirski
2014-06-26 22:58                           ` Dave Hansen
2014-06-26 23:15                             ` Andy Lutomirski
2014-06-27  0:19                               ` Dave Hansen
2014-06-27  0:26                                 ` Andy Lutomirski
2014-06-27 17:34                                   ` Dave Hansen
2014-06-27 17:42                                     ` Dave Hansen
2014-06-27 18:57                                       ` Andy Lutomirski
2014-06-25 21:43                     ` Dave Hansen
2014-06-24  2:53     ` Ren, Qiaowei
2014-06-18  9:44 ` [PATCH v6 03/10] x86, mpx: add macro cpu_has_mpx Qiaowei Ren
2014-06-18  9:57   ` Borislav Petkov
2014-06-18 14:35     ` Dave Hansen
2014-06-18 14:44       ` Borislav Petkov
2014-06-18 14:58         ` Dave Hansen
2014-06-18 15:25           ` Borislav Petkov
2014-06-18 16:17             ` Dave Hansen
2014-06-18 15:00         ` H. Peter Anvin
2014-06-18 15:27           ` Borislav Petkov
2014-06-18 14:59       ` H. Peter Anvin
2014-06-18 16:25         ` Dave Hansen
2014-06-18 17:21           ` Borislav Petkov
2014-06-19 18:02           ` H. Peter Anvin
2014-06-19 18:50             ` Dave Hansen
2014-06-20  3:28               ` H. Peter Anvin
2014-06-18  9:44 ` [PATCH v6 04/10] x86, mpx: hook #BR exception handler to allocate bound tables Qiaowei Ren
2014-06-23 19:54   ` Andy Lutomirski [this message]
2014-06-24  1:53     ` Ren, Qiaowei
2014-07-11 16:23   ` Dave Hansen
2014-06-18  9:44 ` [PATCH v6 05/10] x86, mpx: extend siginfo structure to include bound violation information Qiaowei Ren
2014-06-18  9:44 ` [PATCH v6 06/10] mips: sync struct siginfo with general version Qiaowei Ren
2014-06-18  9:44 ` [PATCH v6 07/10] x86, mpx: decode MPX instruction to get bound violation information Qiaowei Ren
2014-06-18 10:07   ` Borislav Petkov
2014-06-19  1:13     ` Ren, Qiaowei
2014-06-19  6:28       ` Borislav Petkov
2014-06-19  6:53         ` Ren, Qiaowei
2014-06-19 17:04           ` Dave Hansen
2014-06-19 17:32             ` H. Peter Anvin
2014-06-20  3:21               ` Ren, Qiaowei
2014-06-18  9:44 ` [PATCH v6 08/10] x86, mpx: add prctl commands PR_MPX_REGISTER, PR_MPX_UNREGISTER Qiaowei Ren
2014-06-19 20:58   ` Dave Hansen
2014-06-23 20:00   ` Andy Lutomirski
2014-06-23 20:09     ` Dave Hansen
2014-06-23 22:00       ` Andy Lutomirski
2014-06-23 23:42         ` Dave Hansen
2014-06-24  0:01           ` Andy Lutomirski
2014-06-24  0:10             ` Dave Hansen
2014-06-18  9:44 ` [PATCH v6 09/10] x86, mpx: cleanup unused bound tables Qiaowei Ren
2014-06-23 19:57   ` Andy Lutomirski
2014-06-18  9:44 ` [PATCH v6 10/10] x86, mpx: add documentation on Intel MPX Qiaowei Ren
2014-06-18 14:41 ` [PATCH v6 00/10] Intel MPX support Dave Hansen

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