From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 97EB623817E for ; Wed, 22 Apr 2026 13:32:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776864767; cv=none; b=imLK9FWN0TBV6tLnN5MYaVtCN93mX8N63dHRySsz3WVZKpJsKxpLa3QddPYMqn3eXsCPse6yKGiS9IHBRMoUDG8U1o0zuD2SCULRm69U3PCzQjUSBjTIOOl/O00AqdgkbH2GZnb7WfYqfyqkzlBrHekoLIqy1yevBgyfsIs1rok= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776864767; c=relaxed/simple; bh=YXsCrcloyAS6Z2ucKYRhA+5bQY8YXgApvqqeltML85k=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=FZ9glMAY/tRTuC1k80qVi+3dsWXGlX/B5AfH9syb00R/mi1TV2osFto7ElIRHWHux4PMUFGU759KczkKbpd47usohDxxPoysFd0bFOj0+27a5dJ8H0Dw7eLWXXoHlHWdZkqItBSkRQ1cVi6lzfD38vu2DAly3mV4Hzf8KfyEB78= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=a7aCW5+J; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="a7aCW5+J" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 695432454; Wed, 22 Apr 2026 06:32:39 -0700 (PDT) Received: from [10.57.32.235] (unknown [10.57.32.235]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 01FD53FBD2; Wed, 22 Apr 2026 06:32:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776864764; bh=YXsCrcloyAS6Z2ucKYRhA+5bQY8YXgApvqqeltML85k=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=a7aCW5+J+7SKt6IxdKYD1bUqpHeg6nLUIgs3zYF89cI6Z5omtHQOiMz35OL0oGqby 2Zsyay2BbI9peAyJttIr9x75umpBZg0q8QZPFvxog4KbxZUlQXk/F7zpA+PqJydsHI Lt43D0MGdlkRayFpaTZpedX0qQjaixMXOl0xn3So= Message-ID: <53a66bbd-7ed5-41d9-a15e-af17f292dea1@arm.com> Date: Wed, 22 Apr 2026 10:34:42 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/8] drm/panthor: Store IRQ register base iomem pointer in panthor_irq To: Karunika Choo , dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org References: <20260412142951.2309135-1-karunika.choo@arm.com> <20260412142951.2309135-5-karunika.choo@arm.com> From: Steven Price Content-Language: en-GB In-Reply-To: <20260412142951.2309135-5-karunika.choo@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/04/2026 15:29, Karunika Choo wrote: > Update common IRQ handling code to work from an IRQ-local iomem base > instead of referencing block-specific interrupt register offsets. > > Store the interrupt base address iomem pointer in struct panthor_irq and > switch the shared IRQ helpers to use generic INT_* offsets from that > local base. This removes the need for each caller to expose absolute IRQ > register addresses while keeping the common IRQ flow unchanged. > > No functional change intended. > > v2: > - Change IRQ request function to accept an iomem pointer instead of > computing it from an offset argument. > > Signed-off-by: Karunika Choo One minor comment below... > --- > drivers/gpu/drm/panthor/panthor_device.h | 32 ++++++++++++++-------- > drivers/gpu/drm/panthor/panthor_fw.c | 5 ++-- > drivers/gpu/drm/panthor/panthor_fw_regs.h | 2 ++ > drivers/gpu/drm/panthor/panthor_gpu.c | 6 ++-- > drivers/gpu/drm/panthor/panthor_gpu_regs.h | 3 ++ > drivers/gpu/drm/panthor/panthor_mmu.c | 5 ++-- > drivers/gpu/drm/panthor/panthor_mmu_regs.h | 3 ++ > drivers/gpu/drm/panthor/panthor_pwr.c | 6 ++-- > 8 files changed, 42 insertions(+), 20 deletions(-) > [...] > @@ -1470,7 +1470,8 @@ int panthor_fw_init(struct panthor_device *ptdev) > if (irq <= 0) > return -ENODEV; > > - ret = panthor_request_job_irq(ptdev, &fw->irq, irq, 0); > + ret = panthor_request_job_irq(ptdev, &fw->irq, irq, 0, > + ptdev->iomem + JOB_INT_BASE); > if (ret) { > drm_err(&ptdev->base, "failed to request job irq"); > return ret; [..] > @@ -162,7 +162,9 @@ int panthor_gpu_init(struct panthor_device *ptdev) > if (irq < 0) > return irq; > > - ret = panthor_request_gpu_irq(ptdev, &ptdev->gpu->irq, irq, GPU_INTERRUPTS_MASK); > + ret = panthor_request_gpu_irq(ptdev, &ptdev->gpu->irq, irq, > + GPU_INTERRUPTS_MASK, > + ptdev->iomem + GPU_INT_BASE); > if (ret) > return ret; > [...] > @@ -3229,7 +3229,8 @@ int panthor_mmu_init(struct panthor_device *ptdev) > return -ENODEV; > > ret = panthor_request_mmu_irq(ptdev, &mmu->irq, irq, > - panthor_mmu_fault_mask(ptdev, ~0)); > + panthor_mmu_fault_mask(ptdev, ~0), > + ptdev->iomem + MMU_INT_BASE); > if (ret) > return ret; > [...] > diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c > index aafb0c5c7d23..11c43de1ddd5 100644 > --- a/drivers/gpu/drm/panthor/panthor_pwr.c > +++ b/drivers/gpu/drm/panthor/panthor_pwr.c > @@ -70,7 +70,7 @@ static void panthor_pwr_irq_handler(struct panthor_device *ptdev, u32 status) > } > spin_unlock(&ptdev->pwr->reqs_lock); > } > -PANTHOR_IRQ_HANDLER(pwr, PWR, panthor_pwr_irq_handler); > +PANTHOR_IRQ_HANDLER(pwr, panthor_pwr_irq_handler); > > static void panthor_pwr_write_command(struct panthor_device *ptdev, u32 command, u64 args) > { > @@ -464,7 +464,9 @@ int panthor_pwr_init(struct panthor_device *ptdev) > if (irq < 0) > return irq; > > - err = panthor_request_pwr_irq(ptdev, &pwr->irq, irq, PWR_INTERRUPTS_MASK); > + err = panthor_request_pwr_irq( > + ptdev, &pwr->irq, irq, PWR_INTERRUPTS_MASK, > + ptdev->iomem + GPU_CONTROL_BASE + PWR_CONTROL_BASE); This one is the odd one out because it adds GPU_CONTROL_BASE put the other panthor_request_xxx_irq() calls don't. Sashiko also points out that there's an argument these should all be using ptdev->gpu->iomem in the final refactor. Thanks, Steve > if (err) > return err; >