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X-OriginatorOrg: opensource.cirrus.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2025 16:27:14.1948 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37441f9b-8b0f-4892-eb66-08de06878a59 X-MS-Exchange-CrossTenant-Id: bec09025-e5bc-40d1-a355-8e955c307de8 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=bec09025-e5bc-40d1-a355-8e955c307de8;Ip=[84.19.233.75];Helo=[edirelay1.ad.cirrus.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR19MB5746 X-Proofpoint-ORIG-GUID: QxOY2FbbAp1hFQCWDBOZMH7HG64zgu66 X-Proofpoint-GUID: QxOY2FbbAp1hFQCWDBOZMH7HG64zgu66 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA4MDExNiBTYWx0ZWRfXzDfuSQeP0mbq P+ulWBPhgS5v0MGAshtljfn/5F+4cFjraNyidGkrrVuyp+VmPBiMg+yX+NG1rUhkIUaStk4ls/L t26F2pWS452OdG/ELxihTT0ucMK+NdGa2KNHyGoXV31IoEBJ5WGMoGE5unVK0AJOt9m0nWFRDjC OAa6tK7jDbql7wVpeze1YBn10uh8b5ovNyXjbMQ0hDox6qtH1c/Mj8V1XDtjDtcmWFW9S4ai82z 9BnaeJS9az9ID2NexZlrQvGL4bZJW0ERlO/WHh4cBuAHvxDSM/I/kGnLGLJaYAvmOBR6rhBP4Rf qqwW5cyztD/8tMzVLMRw/0/mDoU2BqA67tBgNVruS5x2+7qHDxRtltZv2A7MohAHqXfxDJw/AGI 28HAFrzQN+bzBZaAxOAh2hrt0+6ttg== X-Authority-Analysis: v=2.4 cv=ePceTXp1 c=1 sm=1 tr=0 ts=68e690e8 cx=c_pps a=9hhwatWKa7/vLw/BZzsOGQ==:117 a=h1hSm8JtM9GN1ddwPAif2w==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=z/mQ4Ysz8XfWz/Q5cLBRGdckG28=:19 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s63m1ICgrNkA:10 a=RWc_ulEos4gA:10 a=U2_j2L6mtO50HzZEORoA:9 a=QEXdDO2ut3YA:10 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-Spam-Reason: safe On 08/10/2025 5:04 pm, Brian Sune wrote: > In previous WM8978 codec driver versions, wm8978_set_dai_clkdiv > might not have been called for BCLK, leaving the bit clock > divider unconfigured. This could cause incorrect or unstable audio > clocks depending on sample rate and word length. > > This patch adds a check in wm8978_hw_params: if the BCLK divider > has not been set via wm8978_set_dai_clkdiv, it is dynamically > calculated and configured at runtime. > This ensures that BCLK is always correctly set, whether the > machine driver configures it explicitly or not. > > Apart from this core patch, due to request from Mark Brown and > Charles Keepax. Overclock BCLK setup is applied, and dropped the > possible lowest error BCLK result. Selecting a lowest-error rate is not valid I2S. You must have enough BCLK cycles to send all the data. If number of BCLK cycles < number of sample bits you cannot send all the sample bits. So that would be an incorrect setup. > On top of the overclocking, Using a higher BCLK is valid I2S. In fact, it is exactly defined in the I2S specification that there can be more BCLK cycles than data bits and the RX end should ignore extra cycles. > warning message is given to user as a reminding. Warning the user that you selected the correct BCLK is strange. > This patch author do not agree with this design nor > concept from first place! For example if you are sending stereo 16-bit samples at 48 kHz you must have a BCLK at least 48000 * 16 * 2 = 1536000 Hz. If the _nearest_ BCLK is < 1536000 you don't have enough clock cycles to send all the sample bits.