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X-CSE-ConnectionGUID: VUHqm79tTvK7tLON3qaW/g== X-CSE-MsgGUID: Y3UyqmeAQ6a6vxXfLCXbEA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41549021" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41549021" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 08:26:46 -0800 X-CSE-ConnectionGUID: ILa6z2FFSoeyqMIr75+u2g== X-CSE-MsgGUID: coYb8hJuTomn81C6XwiwAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,257,1725346800"; d="scan'208";a="84049655" Received: from tfalcon-desk.amr.corp.intel.com (HELO [10.124.221.97]) ([10.124.221.97]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 08:26:45 -0800 Message-ID: <53c918b4-2e03-4f68-b3f3-d18f62d5805c@intel.com> Date: Mon, 4 Nov 2024 08:26:44 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature To: "Shah, Amit" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-doc@vger.kernel.org" , "x86@kernel.org" Cc: "corbet@lwn.net" , "boris.ostrovsky@oracle.com" , "kai.huang@intel.com" , "pawan.kumar.gupta@linux.intel.com" , "jpoimboe@kernel.org" , "dave.hansen@linux.intel.com" , "daniel.sneddon@linux.intel.com" , "Lendacky, Thomas" , "seanjc@google.com" , "mingo@redhat.com" , "pbonzini@redhat.com" , "tglx@linutronix.de" , "Moger, Babu" , "Das1, Sandipan" , "hpa@zytor.com" , "peterz@infradead.org" , "bp@alien8.de" , "Kaplan, David" References: <20241031153925.36216-1-amit@kernel.org> <20241031153925.36216-2-amit@kernel.org> <05c12dec-3f39-4811-8e15-82cfd229b66a@intel.com> <4b23d73d450d284bbefc4f23d8a7f0798517e24e.camel@amd.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/4/24 08:13, Shah, Amit wrote: > I want to justify that not setting X86_FEATURE_RSB_CTXSW is still doing > the right thing, albeit in hardware. Let's back up a bit. In the kernel, we have security concerns if RSB contents remain across context switches. If process A's RSB entries are left and then process B uses them, there's a problem. Today, we mitigate that issue with manual kernel RSB state zapping on context switches (X86_FEATURE_RSB_CTXSW). You're saying that this fancy new ERAPS feature includes a new mechanism to zap RSB state. But that only triggers "each time a TLB flush happens". So what you're saying above is that you are concerned about RSB contents sticking around across context switches. But instead of using X86_FEATURE_RSB_CTXSW, you believe that the new TLB-flush-triggered ERAPS flush can be used instead. Are we all on the same page so far? I think you're wrong. We can't depend on ERAPS for this. Linux doesn't flush the TLB on context switches when PCIDs are in play. Thus, ERAPS won't flush the RSB and will leave bad state in there and will leave the system vulnerable. Or what am I missing?