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Both run at 100 kHz, which is what the vendor devicetree uses. i2c1 is internal to the board and carries only the PMIC, which is why it is the one already at 400 kHz. Signed-off-by: Rudi Heitbaum --- .../boot/dts/freescale/imx8mq-phanbell.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts index 4ad206f5a9d1..58f7276eb557 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts @@ -260,6 +260,20 @@ ldo7: LDO7 { }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -367,6 +381,20 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 -- 2.53.0