From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752715AbbHTOZ6 (ORCPT ); Thu, 20 Aug 2015 10:25:58 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:47693 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751738AbbHTOZ5 (ORCPT ); Thu, 20 Aug 2015 10:25:57 -0400 X-AuditID: cbfee68f-f793b6d000005f66-da-55d5e37216a8 Date: Thu, 20 Aug 2015 14:25:54 +0000 (GMT) From: Sarbojit Ganguly Subject: Re: Re: Re: [PATCH] arm: Adding support for atomic half word exchange To: "linux@arm.linux.org.uk" , Will Deacon Cc: Sarbojit Ganguly , Catalin Marinas , "linux-arm-kernel@lists.infradead.org" , SHARAN ALLUR , VIKRAM MUPPARTHI , "peterz@infradead.org" , "Waiman.Long@hp.com" , "linux-kernel@vger.kernel.org" , "torvalds@linux-foundation.org" Reply-to: ganguly.s@samsung.com MIME-version: 1.0 X-MTR: 20150820142334293@ganguly.s Msgkey: 20150820142334293@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20150820142334293@ganguly.s X-ParentMTR: X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general Content-type: text/plain; charset=windows-1252 MIME-version: 1.0 Message-id: <540319746.1862071440080751898.JavaMail.weblogic@ep2mlwas01b> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKIsWRmVeSWpSXmKPExsWyRsSkTrf48dVQg3cXOCwu75rD5sDo8XmT XABjFJdNSmpOZllqkb5dAlfGltfrmAouSFa8mjuRsYHxh0QXIweHkICKRN+kCBBTQsBE4sy0 4C5GTiBTTOLCvfVsXYxcQBVLGSW23TjNBpEwkZi4aiUTRGIOo8SN819YQBIsAqoSb5+9Biti E9CXOL3/JROILSzgJ/H6+RpmEFtEIEbi1b0usKnMAq+YJf42nAMrEhKQl2h/sR3M5hUQlDg5 8wkLxDYliQMn7zNCxJUlPk67xwoRl5NYMvUyE4TNKzGj/SkLTHzaV4hlEgLSEudnbWCEeWfx 98dQcX6JY7d3QPUKSEw9cxCqRl1i6b9vUDafxJqFb1lg6nedWs4Ms6th4292CFtCYmvLE7B7 mAUUJaZ0P2SHsA0kjiyaw4ruF14BT4nDq74zgzwvITCRQ+LKzn72CYxKs5DUzUIyaxaSWchq FjCyrGIUTS1ILihOSi8y1itOzC0uzUvXS87P3cQITA2n/z3r38F494D1IUYBDkYlHt4LwldD hVgTy4orcw8xmgIjaiKzlGhyPjAB5ZXEGxqbGVmYmpgaG5lbmimJ8y6U+hksJJCeWJKanZpa kFoUX1Sak1p8iJGJg1OqgfGEnRyLt13U55CUm2+zH4nMa1IVkV8SLvHpsO6Gbb086zp7Vx+P mRKjVb3zohzXbuOph1nmhjB4zL3Tlmu8fAXnnKuHg60P3JzzeJbF0pU5TAfUtmh7ftWeuaLz x733k1Y62J112Hr83z/Ttc4C59/c5rH5sKnFMPO1HPe+vTPE9lc9LHsq/kpGiaU4I9FQi7mo OBEAOjgJrwgDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOKsWRmVeSWpSXmKPExsVy+t/tPt2ix1dDDR7csra4vGsOmwOjx+dN cgGMUWk2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUBD lRTKEnNKgUIBicXFSvp2NkX5pSWpChn5xSW2StGG5kZ6RgZ6pkZ6hqaxVoYGBkamQDUJaRlb Xq9jKrggWfFq7kTGBsYfEl2MHBxCAioSfZMiuhg5OSQETCQmrlrJBGGLSVy4t56ti5ELqGQO o8SN819YQBIsAqoSb5+9ZgOx2QT0JU7vfwnWICzgJ/H6+RpmEFtEIEbi1b0usGZmgVfMEn8b zoEVCQnIS7S/2A5m8woISpyc+YQFYpuSxIGT9xkh4soSH6fdY4WIy0ksmXoZ6iJeiRntT1lg 4tO+QiyTEJCWOD9rAyPM1Yu/P4aK80scu70DqldAYuqZg1A16hJL/32Dsvkk1ix8ywJTv+vU cmaYXQ0bf7ND2BISW1uegN3DLKAoMaX7ITuEbSBxZNEcVnS/8Ap4Shxe9Z15AqPsLCSpWUja ZyFpR1azgJFlFaNoakFyQXFSeoWJXnFibnFpXrpecn7uJkZwInq2ZAdjwwXrQ4wCHIxKPLwa YldDhVgTy4orcw8xSnAwK4nw7r8BFOJNSaysSi3Kjy8qzUktPsRoCoy2icxSosn5wCSZVxJv aGxibmpsamFgaG5upiTO+/9cboiQQHpiSWp2ampBahFMHxMHp1QD47RQhZhrMX/T/x/+Mz1j r8w5l+JPamd+vtSYM2lnrb6GZ4ZS94eTlfb3zz7PtN1vcO34/ZiNcUJbVDO+s608OvFiRNGn /CfSzImy8y2mnpOK/n6PX8shIPfPqyDJvPtf98rv/tPc3/lAmsvZcql4Z7JUf+2S7tNcClOr nQMkO5nOta5JddnJqcRSnJFoqMVcVJwIAH9w14RaAwAA DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t7KEQ32Q028247 >> My apologies, the e-mail editor was not configured properly. >> CC'ed to relevant maintainers and reposting once again with proper formatting. >> >> Since 16 bit half word exchange was not there and MCS based qspinlock >> by Waiman's xchg_tail() requires an atomic exchange on a half word, >> here is a small modification to __xchg() code to support the exchange. >> ARMv6 and lower does not have support for LDREXH, so we need to make >> sure things do not break when we're compiling on ARMv6. >> >> Signed-off-by: Sarbojit Ganguly > >> --- >> arch/arm/include/asm/cmpxchg.h | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/arch/arm/include/asm/cmpxchg.h >> b/arch/arm/include/asm/cmpxchg.h index 1692a05..547101d 100644 >> --- a/arch/arm/include/asm/cmpxchg.h >> +++ b/arch/arm/include/asm/cmpxchg.h >> @@ -50,6 +50,24 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size >> : "r" (x), "r" (ptr) >> : "memory", "cc"); >> break; >> +#if !defined (CONFIG_CPU_V6) >> + /* >> + * Halfword exclusive exchange >> + * This is new implementation as qspinlock >> + * wants 16 bit atomic CAS. >> + * This is not supported on ARMv6. >> + */ >I don't think you need this comment. We don't use qspinlock on arch/arm/. Yes, till date mainline ARM does not support but I've ported Qspinlock on ARM hence I think that comment might be required. >> + case 2: >> + asm volatile("@ __xchg2\n" >> + "1: ldrexh %0, [%3]\n" >> + " strexh %1, %2, [%3]\n" >> + " teq %1, #0\n" >> + " bne 1b" >> + : "=&r" (ret), "=&r" (tmp) >> + : "r" (x), "r" (ptr) >> + : "memory", "cc"); >> + break; >> +#endif >> case 4: >> asm volatile("@ __xchg4\n" >> "1: ldrex %0, [%3]\n" >We have the same issue with the byte exclusives, so I think you need to extend the guard you're adding to cover that case too (which is a bug in current mainline). Ok, I will work on this and release a v2 soon. >Will - Sarbojit {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I