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From: Reinette Chatre <reinette.chatre@intel.com>
To: "Drew Fustini" <fustini@kernel.org>,
	"Adrien Ricciardi" <aricciardi@baylibre.com>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Atish Patra" <atish.patra@linux.dev>,
	"Babu Moger" <babu.moger@amd.com>,
	"Ben Horgan" <ben.horgan@arm.com>,
	"Borislav Petkov" <bp@alien8.de>,
	"Chen Pei" <cp0613@linux.alibaba.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	"Dave Martin" <Dave.Martin@arm.com>,
	"Fenghua Yu" <fenghuay@nvidia.com>,
	"Gong Shuai" <gong.shuai@sanechips.com.cn>,
	"Gong Shuai" <gsh517@gmail.com>,
	guo.wenjia23@zte.com.cn, "James Morse" <james.morse@arm.com>,
	"Kornel Dulęba" <mindal@semihalf.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	liu.qingtao2@zte.com.cn,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <pjw@kernel.org>,
	"Peter Newman" <peternewman@google.com>,
	"Radim Krčmář" <radim.krcmar@oss.qualcomm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Sunil V L" <sunilvl@oss.qualcomm.com>,
	"Tony Luck" <tony.luck@intel.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"yunhui cui" <cuiyunhui@bytedance.com>,
	"Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>,
	Zeng Heng <zengheng@picoheart.com>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<x86@kernel.org>, <devicetree@vger.kernel.org>,
	<linux-doc@vger.kernel.org>
Subject: Re: [PATCH v11 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask
Date: Thu, 12 Nov 2026 08:24:15 -0800	[thread overview]
Message-ID: <54079068-9f33-4ea3-91dc-c5c82e37a70f@intel.com> (raw)
In-Reply-To: <avOmHFcy/yFOr9YX@x1>

Hi Drew,

On 11/10/26 3:17 PM, Drew Fustini wrote:
> On Sun, Nov 08, 2026 at 03:20:51PM -0800, Drew Fustini wrote:
>> Wire CBQRI capacity controllers into resctrl as the L2 and L3 cache
>> resources.
>>
>> resctrl exposes a single capacity mask per resource, so when more than
>> one capacity controller backs a cache level they must report the same
>> number of capacity blocks. The same holds for the other capabilities
>> resctrl exposes once per resource. A level whose controllers disagree
>> is left unexposed. Other levels are unaffected.
>>
>> The set of controllers backing each level is fixed when resctrl is set
>> up at late_initcall. Control domains are created in the cpuhp online
>> callback and keyed on the onlining CPU's cache id from cacheinfo, so a
>> CPU that is offline at probe time still joins its domain once it comes
>> online, provided a controller for its cache is in that set.
>>
>> A CPU whose cache has no controller, or whose domain cannot be created,
>> still comes online. It is left out of that level and a warning is
>> logged, since bringing the CPU up matters more than controlling its
>> cache traffic. A domain is published on the ctrl_domains RCU list only
>> after it is fully initialized and brought online, and removed from the
>> list before it is taken offline, following the documented safe
>> traversal rules.
>>
>> Tested-by: Chen Pei <cp0613@linux.alibaba.com>
>> Acked-by: Reinette Chatre <reinette.chatre@intel.com>
> 
> Hi Reinette, I still need to get more reviews on this series, but I
> wanted to check if your expectation is that all the patches in this
> series should be merged through arch/riscv?
Here I'll defer to what works best for the architecture and tip maintainers.

We still need to create a strategy with the respective architecture maintainers 
for how conflicts between the resctrl filesystem and architecture drivers should
to be resolved. Without encountering this yet this may end up evolving based on
the conflicts encountered. Even so, I think it is worthwhile to at least start the
conversation with the architecture maintainers to introduce that this driver
may need extra support/coordination during merge window.

Reinette

  reply	other threads:[~2026-11-12 16:24 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-08 23:20 [PATCH v11 0/5] riscv: Add initial CBQRI resctrl support Drew Fustini
2026-11-08 23:20 ` [PATCH v11 1/5] riscv_cbqri: Add capacity controller core Drew Fustini
2026-11-12 16:14   ` Radim Krčmář
2026-11-08 23:20 ` [PATCH v11 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
2026-11-10 23:17   ` Drew Fustini
2026-11-12 16:24     ` Reinette Chatre [this message]
2026-11-08 23:20 ` [PATCH v11 3/5] riscv_cbqri: Make RESCTRL_FS available on RISC-V Drew Fustini
2026-11-08 23:20 ` [PATCH v11 4/5] dt-bindings: riscv: Add binding for CBQRI controllers Drew Fustini
2026-11-08 23:20 ` [PATCH v11 5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver Drew Fustini
2026-11-09 13:06 ` [PATCH v11 0/5] riscv: Add initial CBQRI resctrl support Zeng Heng

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