Re: [GIT PULL] x86/urgent for v5.11-rc7

[Dave Hansen <dave.hansen@intel.com>]

On 2/7/21 10:15 AM, Linus Torvalds wrote:
> On Sun, Feb 7, 2021 at 9:58 AM Borislav Petkov <bp@suse.de> wrote:
>> It probably is an item on some Intel manager's to-enable list. So far,
>> the CET enablement concentrates only on userspace but dhansen might know
>> more about future plans. CCed.
> I think the new Ryzen 5000 series also supports CET, but I don't have
> any machines to check.

Intel wraps up Shadow Stacks and Indirect Branch Tracking (IBT) under
the CET umbrella, although they can be implemented totally independently.

I actually forget about the IBT half most of the time because the kernel
code to implement userspace support is a much lighter lift than shadow
stacks.

My understanding is that AMD has documented support for Shadow Stacks:

	https://www.amd.com/system/files/TechDocs/24592.pdf

But has not yet released any documentation about IBT.  IBT seems to be
Intel-only, at least in the short term.  There may be more, but the
"Tiger Lake" CPUs are the only ones I know of off the top of my head
that are in the wild:

> https://ark.intel.com/content/www/us/en/ark/products/208661/intel-core-i7-1160g7-processor-12m-cache-up-to-4-40-ghz-with-ipu.html