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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45dd3aadbcesm15507775e9.17.2025.09.04.07.56.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 07:56:37 -0700 (PDT) Message-ID: <548b3a0d-01c0-46c3-aad0-a820447f86dc@linaro.org> Date: Thu, 4 Sep 2025 15:56:33 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] arm64: dts: qcom: sc8280xp: Add OPP table for CCI hosts To: Konrad Dybcio , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, Konrad Dybcio References: <20250904-topic-cci_updates-v1-0-d38559692703@oss.qualcomm.com> <20250904-topic-cci_updates-v1-5-d38559692703@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20250904-topic-cci_updates-v1-5-d38559692703@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 04/09/2025 15:31, Konrad Dybcio wrote: > From: Konrad Dybcio > > The CCI hosts have both frequency and voltage requirements (which > happen to be common across instances on a given SoC, at least so far). > > Express them by introducing an OPP table and linking it to the hosts. > > Signed-off-by: Konrad Dybcio > --- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 18b5cb441f955f7a91204376e05536b203f3e28b..c396186317d49f411d7162771a358563329a02a4 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -391,6 +391,15 @@ memory@80000000 { > reg = <0x0 0x80000000 0x0 0x0>; > }; > > + cci_opp_table: opp-table-cci { > + compatible = "operating-points-v2"; > + > + opp-37500000 { > + opp-hz = /bits/ 64 <37500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + }; > + > cpu0_opp_table: opp-table-cpu0 { > compatible = "operating-points-v2"; > opp-shared; > @@ -4181,6 +4190,7 @@ cci0: cci@ac4a000 { > "cpas_ahb", > "cci"; > > + operating-points-v2 = <&cci_opp_table>; > power-domains = <&camcc TITAN_TOP_GDSC>; > > pinctrl-0 = <&cci0_default>; > @@ -4222,6 +4232,7 @@ cci1: cci@ac4b000 { > "cpas_ahb", > "cci"; > > + operating-points-v2 = <&cci_opp_table>; > power-domains = <&camcc TITAN_TOP_GDSC>; > > pinctrl-0 = <&cci1_default>; > @@ -4262,6 +4273,8 @@ cci2: cci@ac4c000 { > "slow_ahb_src", > "cpas_ahb", > "cci"; > + > + operating-points-v2 = <&cci_opp_table>; > power-domains = <&camcc TITAN_TOP_GDSC>; > > pinctrl-0 = <&cci2_default>; > @@ -4303,6 +4316,7 @@ cci3: cci@ac4d000 { > "cpas_ahb", > "cci"; > > + operating-points-v2 = <&cci_opp_table>; > power-domains = <&camcc TITAN_TOP_GDSC>; > > pinctrl-0 = <&cci3_default>; > Reviewed-by: Bryan O'Donoghue