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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-396abf66ea9sm3570671fa.2.2026.06.02.15.07.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Jun 2026 15:07:17 -0700 (PDT) Message-ID: <54904b61-222d-4600-ad4c-c03a9952d337@linaro.org> Date: Wed, 3 Jun 2026 01:07:16 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver To: Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260523-x1e-csi2-phy-v8-0-a85668459521@linaro.org> <20260523-x1e-csi2-phy-v8-2-a85668459521@linaro.org> From: Vladimir Zapolskiy In-Reply-To: <20260523-x1e-csi2-phy-v8-2-a85668459521@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 5/23/26 05:48, Bryan O'Donoghue wrote: > Add a new MIPI CSI2 driver in DPHY mode initially. The entire set of > existing CAMSS CSI PHY init sequences are imported in order to save time > and effort in later patches. > > The following devices are supported in this drop: > "qcom,x1e80100-csi2-phy" > > In-line with other PHY drivers the process node is included in the name. > Data-lane and clock lane positioning and polarity selection via newly > amended struct phy_configure_opts_mipi_dphy{} is supported. > > The Qualcomm 3PH class of PHYs can do both DPHY and CPHY mode. For now only > DPHY is supported. > > In porting some of the logic over from camss-csiphy*.c to here its also > possible to rationalise some of the code. > > In particular use of regulator_bulk and clk_bulk as well as dropping the > seemingly useless and unused interrupt handler. > > The PHY sequences and a lot of the logic that goes with them are well > proven in CAMSS and mature so the main thing to watch out for here is how > to get the right sequencing of regulators, clocks and register-writes. > > The register init sequence table is imported verbatim from the existing > CAMSS csiphy driver. A follow-up series will rework the table to extract > the repetitive per-lane pattern into a loop. > > Signed-off-by: Bryan O'Donoghue <> > +static int phy_qcom_mipi_csi2_parse_routing(struct mipi_csi2phy_device *csi2phy) > +{ > + struct mipi_csi2phy_stream_cfg *stream_cfg = &csi2phy->stream_cfg; > + u32 lane_polarities[CSI2_MAX_DATA_LANES + 1]; > + u32 data_lanes[CSI2_MAX_DATA_LANES]; > + struct device *dev = csi2phy->dev; > + struct fwnode_handle *ep; > + int num_polarities; > + int num_data_lanes; > + u32 clock_lane; > + int i, ret; > + > + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 1, 0, > + FWNODE_GRAPH_ENDPOINT_NEXT); > + if (ep) { > + fwnode_handle_put(ep); > + dev_err(dev, "DPHY split mode is not supported\n"); > + return -EOPNOTSUPP; > + } > + > + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0); > + if (!ep) { > + dev_err(dev, "Missing port@0\n"); > + return -ENODEV; > + } > + > + num_data_lanes = fwnode_property_count_u32(ep, "data-lanes"); > + if (num_data_lanes < 1 || num_data_lanes > CSI2_MAX_DATA_LANES) { > + ret = -EINVAL; > + dev_err(dev, "Invalid data-lanes count: %d\n", num_data_lanes); > + goto out_put; > + } > + stream_cfg->num_data_lanes = num_data_lanes; > + > + ret = fwnode_property_read_u32_array(ep, "data-lanes", data_lanes, > + stream_cfg->num_data_lanes); > + if (ret) { > + dev_err(dev, "Failed to read data-lanes: %d\n", ret); > + goto out_put; > + } > + > + ret = fwnode_property_read_u32(ep, "clock-lanes", &clock_lane); > + if (ret) { > + clock_lane = CSI2_DEFAULT_CLK_LN; > + dev_info(dev, "Using default clock-lane %d\n", > + CSI2_DEFAULT_CLK_LN); Why CSI2_DEFAULT_CLK_LN is set to 7, what does it mean and how is it used? Since "7" is a meaningless number in the context, I believe it's practically not used at all, and if so, 'clock-lanes' property should be just removed. > + } -- Best wishes, Vladimir