From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758792AbbCDMRo (ORCPT ); Wed, 4 Mar 2015 07:17:44 -0500 Received: from service87.mimecast.com ([91.220.42.44]:43350 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750830AbbCDMRm convert rfc822-to-8bit (ORCPT ); Wed, 4 Mar 2015 07:17:42 -0500 Message-ID: <54F6F7E3.40302@arm.com> Date: Wed, 04 Mar 2015 12:17:39 +0000 From: "Suzuki K. Poulose" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: Sudeep Holla , "linux-arm-kernel@lists.infradead.org" CC: "nico@linaro.org" , "b.zolnierkie@samsung.com" , "kgene@kernel.org" , "a.kesavan@samsung.com" , "arnd@arndb.de" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Liviu Dudau , Lorenzo Pieralisi , Pawel Moll , "olof@lixom.net" , Punit Agrawal , Will Deacon , Catalin Marinas Subject: Re: [PATCH v2 0/5] arm-cci400: PMU monitoring support on ARM64 References: <1425295754-13376-1-git-send-email-suzuki.poulose@arm.com> <54F5DA8C.7080609@arm.com> In-Reply-To: <54F5DA8C.7080609@arm.com> X-OriginalArrivalTime: 04 Mar 2015 12:17:40.0394 (UTC) FILETIME=[359628A0:01D05675] X-MC-Unique: 115030412174104501 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/03/15 16:00, Sudeep Holla wrote: > > > On 02/03/15 11:29, Suzuki K. Poulose wrote: >> From: "Suzuki K. Poulose" >> >> This series enables the PMU monitoring support for CCI400 on ARM64. >> The existing CCI400 driver code is a mix of PMU driver and the MCPM >> driver code. The MCPM driver is only used on ARM(32) and contains >> arm32 assembly and hence can't be built on ARM64. This patch splits >> the code to >> >> - ARM_CCI400_PORT_CTRL driver - depends on ARM && V7 >> - ARM_CCI400_PMU driver >> >> Accessing the Peripheral ID2 register(PID2) on CCI-400, to detect >> the revision of the chipset, is a secure operation. Hence, it prevents >> us from running this on non-secure platforms. The issue is overcome by >> explicitly mentioning the revision number of the CCI PMU in the device tree >> binding. The device-tree binding has been updated with the new bindings. >> >> i.e, arm-cci-400-pmu,r0 => revision 0 >> arm-cci-400-pmu,r1 => revision 1 >> arm-cci-400-pmu => (old) DEPRECATED >> >> The old binding has been DEPRECATED and must be used only on ARM32 >> system with secure access. We don't have a reliable dynamic way to detect >> if the system is running secure. This series tries to use the best safe >> method by relying on the availability of MCPM(as it was prior to the series). >> It is upto the MCPM platform driver to decide, if the system is secure before >> it goes ahead and registers its drivers and pokes the CCI. This series doesn't >> address/solve the problem of MCPM. I will be happy to use a better approach, >> if there is any. >> >> Tested on (non-secure)TC2 and Juno. >> > > For the series: > Tested-by: Sudeep Holla (on secure/MCPM TC2) > Thanks a lot for the testing Suzuki