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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ot3N_XX5CLw74VIGe9uTb9uEa4uzRg_A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE5MDE1MSBTYWx0ZWRfXxIsBKl1mrIQY 61oSsKpf9qSM38JjWSMU8euSrV6jho9b3BaX02ksZ9FhXk9W7cGMs+yNiSJknG5mNkmhPRgHPTR C6XHyBBNkonzZYKW4gviTjNhotK5ZOla0oUoehLYTNUxoFPx9ZhLqlQymrmSmM6gksQGqwYsV5A EanTlUiDF2h6XBFb/ttGeqPcJ58q/2iFRA8C7Xh8ND/rrjGHl86SISeFJUefW9mk8xeF5/GNwOf cVOiSf5XdrEZGm9TukdcmnX7DPEkR4tHFhQCQY7BReUH7V5fJ+9HYejpbJT4KzsiEFO0IuCUlMd aLfIuBI0gxvIpF0RKxIu4dJDZWXCRK4OSwzRTe/F/JAvQF346qy1Xf6TXPpZVppUGr4Fo9wXq4L Q7cyvE1DBZeJptQUfk/OxWGAKgxH3ur9TV2KpS8pJE14ORLMdD1WDTjIm35wHX3Kr1//spfMn5T 2bP6YlvJ7vym5WmBzVg== X-Proofpoint-Spam-Info: AW1haW4tMjYwODE5MDE1MSBTYWx0ZWRfXyk9OtUmFds/8 FWN1whx+q6xwwn5oPJPyIy7q3PrRYDojGVAsqOmIFYbYdRHG/HWFwkgSvh6J7MNipsFeFZUxV0x JfFTZklSmWpJtWkHEXymZnn80DbGFbE= X-Authority-Analysis: v=2.4 cv=CN8amxrD c=1 sm=1 tr=0 ts=6a8604be cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=5XCNgjhq8C3qGxAi4A93cA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=0pvDCryYY5rQeRNKz3IA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: ot3N_XX5CLw74VIGe9uTb9uEa4uzRg_A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_05,2026-08-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608190151 On 8/18/2026 6:58 PM, Praveen Talari wrote: [...] > +static int spi_geni_panic_notifier(struct notifier_block *nb, > + unsigned long action, void *data) > +{ > + struct spi_geni_master *mas = container_of(nb, struct spi_geni_master, panic_nb); > + struct spi_controller *spi = dev_get_drvdata(mas->dev); > + struct geni_se *se = &mas->se; > + u32 val; > + > + if (!pm_runtime_active(mas->dev)) Not completely sure, but why not NOTIFY_DONE ? we haven't handled anything here. > + return NOTIFY_OK; > + > + if (mas->cur_xfer_mode == GENI_GPI_DMA) { > + dmaengine_terminate_async(mas->tx); > + dmaengine_terminate_async(mas->rx); > + return NOTIFY_OK; > + } > + > + if (!(readl_relaxed(se->base + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE)) Shouldn't this be under FIFO mode check ? As i can see SE DMA mode and GPI mode conditions present but not for FIFO. > + return NOTIFY_OK; > + > + if (!spi->target) { > + geni_se_cancel_m_cmd(se); > + if (!readl_poll_timeout_atomic(se->base + SE_GENI_M_IRQ_STATUS, val, > + val & M_CMD_CANCEL_EN, 10, 50000)) { > + writel_relaxed(M_CMD_CANCEL_EN, se->base + SE_GENI_M_IRQ_CLEAR); > + return NOTIFY_OK; > + } > + } > + > + geni_se_abort_m_cmd(se); why abort is done directly for target device and not for master ? shouldn't be combined with cancel failure ? > + if (!readl_poll_timeout_atomic(se->base + SE_GENI_M_IRQ_STATUS, val, > + val & M_CMD_ABORT_EN, 10, 50000)) > + writel_relaxed(M_CMD_ABORT_EN, se->base + SE_GENI_M_IRQ_CLEAR); > + > + if (mas->cur_xfer_mode == GENI_SE_DMA) { > + writel_relaxed(1, se->base + SE_DMA_TX_FSM_RST); > + readl_poll_timeout_atomic(se->base + SE_DMA_TX_IRQ_STAT, val, > + val & TX_RESET_DONE, 10, 50000); > + writel_relaxed(val, se->base + SE_DMA_TX_IRQ_CLR); > + > + writel_relaxed(1, se->base + SE_DMA_RX_FSM_RST); > + readl_poll_timeout_atomic(se->base + SE_DMA_RX_IRQ_STAT, val, > + val & RX_RESET_DONE, 10, 50000); May be good to declar macro for 10usec and 50msec ? Multiple places it's being used.> + writel_relaxed(val, se->base + SE_DMA_RX_IRQ_CLR); > + } > + > + return NOTIFY_OK; > +} > +[...]