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b=cWCXHnyC4u82w0qdKdaw4g7Pvdb545DMZDjp9bHSn7cMh/tnO48evAlhWbb3SSxgjGvFPbZ4ZqtO26VjExmKwRw0OMjPobXZu+ZQFJriGnEZhiwwu6P4npbnNoD7Jwq10LgNKms0MC74h1psrCK4mCD6S2btsCAyN0h+7vFqH60= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BL3PR12MB6380.namprd12.prod.outlook.com (2603:10b6:208:38d::18) by PH7PR12MB5736.namprd12.prod.outlook.com (2603:10b6:510:1e3::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7698.28; Mon, 24 Jun 2024 15:53:53 +0000 Received: from BL3PR12MB6380.namprd12.prod.outlook.com ([fe80::66cf:5409:24d1:532b]) by BL3PR12MB6380.namprd12.prod.outlook.com ([fe80::66cf:5409:24d1:532b%7]) with mapi id 15.20.7698.025; Mon, 24 Jun 2024 15:53:53 +0000 Message-ID: <550358f7-66d0-441c-abd9-f8edce9a5eb1@amd.com> Date: Mon, 24 Jun 2024 10:53:51 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 6/9] cxl/pci: Add trace logging for CXL PCIe port RAS errors Content-Language: en-US To: Jonathan Cameron Cc: dan.j.williams@intel.com, ira.weiny@intel.com, dave@stgolabs.net, dave.jiang@intel.com, alison.schofield@intel.com, ming4.li@intel.com, vishal.l.verma@intel.com, jim.harris@samsung.com, ilpo.jarvinen@linux.intel.com, ardb@kernel.org, sathyanarayanan.kuppuswamy@linux.intel.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Yazen.Ghannam@amd.com, Robert.Richter@amd.com References: <20240617200411.1426554-1-terry.bowman@amd.com> <20240617200411.1426554-7-terry.bowman@amd.com> <20240620135332.000053f5@Huawei.com> From: Terry Bowman In-Reply-To: <20240620135332.000053f5@Huawei.com> Content-Type: text/plain; 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On 6/20/24 07:53, Jonathan Cameron wrote: > On Mon, 17 Jun 2024 15:04:08 -0500 > Terry Bowman wrote: > >> The cxl_pci driver uses kernel trace functions to log RAS errors for >> endpoints and RCH downstream ports. The same is needed for CXL root ports, >> CXL downstream switch ports, and CXL upstream switch ports. >> >> Add RAS correctable and RAS uncorrectable trace logging functions for >> CXL PCIE ports. >> >> Signed-off-by: Terry Bowman >> --- >> drivers/cxl/core/trace.h | 34 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 34 insertions(+) >> >> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h >> index e5f13260fc52..5cfd9952d88a 100644 >> --- a/drivers/cxl/core/trace.h >> +++ b/drivers/cxl/core/trace.h >> @@ -48,6 +48,23 @@ >> { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ >> ) >> >> +TRACE_EVENT(cxl_port_aer_uncorrectable_error, >> + TP_PROTO(struct device *dev, u32 status), > > By comparison with existing code, why no fe or header > log? Don't exist for ports for some reason? > Serial number of the port might also be useful. > The AER FE and header are the same for ports and the logging needs to be added here. There is no serial number for the ports. Regards, Terry >> + TP_ARGS(dev, status), >> + TP_STRUCT__entry( >> + __string(devname, dev_name(dev)) >> + __field(u32, status) >> + ), >> + TP_fast_assign( >> + __assign_str(devname, dev_name(dev)); >> + __entry->status = status; >> + ), >> + TP_printk("device=%s status='%s'", >> + __get_str(devname), >> + show_uc_errs(__entry->status) >> + ) >> +); >> + >> TRACE_EVENT(cxl_aer_uncorrectable_error, >> TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), >> TP_ARGS(cxlmd, status, fe, hl), >> @@ -96,6 +113,23 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, >> { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ >> ) >> >> +TRACE_EVENT(cxl_port_aer_correctable_error, >> + TP_PROTO(struct device *dev, u32 status), >> + TP_ARGS(dev, status), >> + TP_STRUCT__entry( >> + __string(devname, dev_name(dev)) >> + __field(u32, status) >> + ), >> + TP_fast_assign( >> + __assign_str(devname, dev_name(dev)); >> + __entry->status = status; >> + ), >> + TP_printk("device=%s status='%s'", >> + __get_str(devname), >> + show_ce_errs(__entry->status) >> + ) >> +); >> + >> TRACE_EVENT(cxl_aer_correctable_error, >> TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), >> TP_ARGS(cxlmd, status), >