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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36a5b349d42sm533826a91.15.2026.05.21.04.50.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 May 2026 04:50:35 -0700 (PDT) Message-ID: <55081f4d-f1a9-42c7-a1cd-cdcefc008668@oss.qualcomm.com> Date: Thu, 21 May 2026 19:50:30 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 15/39] drm/msm/dp: Add support for programming p1/p2/p3 register blocks To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-15-b20518dea8de@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=c/ibhx9l c=1 sm=1 tr=0 ts=6a0ef18d cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=AGOk3BmGE1vnVxrgsN4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: WVRH2CfT0QUoD1lb7Py8M6QOPFJoXV0e X-Proofpoint-ORIG-GUID: WVRH2CfT0QUoD1lb7Py8M6QOPFJoXV0e X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIxMDExNyBTYWx0ZWRfX8/XlX3r8jSMP rSJbzs1EKdy5lyLHH/TPgZC/oR8XSt9kd3ypjGpWEMea2rfSAHOi0qYiV/H+aucfW2gr9M4FFVz 3l6huWFUfB6/LL7pJwF6kNaZo0YdCvB9kzbOFXWTITnJXl4hIvrZzZA0kZKOHtzIjDsJQ2l8ecV 4TzRMxAgbQl5esSpnkbOaqMoIl8nEc42yNR64Z7OYeQMHADCKQaGpxjf0Ya1P4lBXFuxQy00Lfe U76GOmnAP3GFBVKd3PNINQPOBfud7YHQyMCiUIufCGDWL+6H2y/CM6C9a+foUv/tMrooPmCQc2S y/dqlhM0s3aUC5epmEh3MJ/85ch5gzZtatZ8vqsJGUnjx29HenAHH4Q9YpWl5UfmlzRijOmmHn0 XlbYioyIaV1HOrEs2WdvHoUbh/lBmjVdb7WXJNm2B0dtqBvB2Ai1GV1qR3jG0oyrDPSpl1n8cnw XmtBAN6DdM573weerhg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-21_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 malwarescore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605210117 On 4/12/2026 2:07 AM, Dmitry Baryshkov wrote: > On Fri, Apr 10, 2026 at 05:33:50PM +0800, Yongxing Mou wrote: >> From: Abhinav Kumar >> >> Add support for additional pixel register blocks (p1, p2, p3) to enable >> 4‑stream MST pixel clocks. Introduce the helper functions msm_dp_read_pn >> and msm_dp_write_pn for pixel register programming. All pixel clocks >> share the same register layout but use different base addresses. >> >> Signed-off-by: Abhinav Kumar >> Signed-off-by: Yongxing Mou >> --- >> drivers/gpu/drm/msm/dp/dp_display.c | 40 ++++++++++++----- >> drivers/gpu/drm/msm/dp/dp_panel.c | 89 ++++++++++++++++++++----------------- >> drivers/gpu/drm/msm/dp/dp_panel.h | 3 +- >> 3 files changed, 79 insertions(+), 53 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c >> index 7984a0f9e938..ff506064a3fa 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_display.c >> +++ b/drivers/gpu/drm/msm/dp/dp_display.c >> @@ -85,8 +85,8 @@ struct msm_dp_display_private { >> void __iomem *link_base; >> size_t link_len; >> >> - void __iomem *p0_base; >> - size_t p0_len; >> + void __iomem *pixel_base[DP_STREAM_MAX]; >> + size_t pixel_len; >> >> int max_stream; >> }; >> @@ -561,7 +561,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) >> goto error_link; >> } >> >> - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->p0_base); >> + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]); >> if (IS_ERR(dp->panel)) { >> rc = PTR_ERR(dp->panel); >> DRM_ERROR("failed to initialize panel, rc = %d\n", rc); >> @@ -769,6 +769,7 @@ int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, >> } >> >> panel->stream_id = stream_id; >> + msm_dp_panel_set_pixel_base(panel, dp->pixel_base[stream_id]); > > Hmmm.... Would it be better to set it up differently? Allocate one panel > per the stream from the beginning and then simply get the first > available panel when required? This would require some minimal resource > manager, but then we won't have to pass dummy register base to the panel > code. Or actually allocate a panel when it is required? Do we need a > panel before atomic_enable()? > In this series, panel come with MST connectors, Because the connectors are dynamically assigned, we don’t know which connector corresponds to which stream, so there stream_id and pixel base address are dynamic. we have 2 optionals here: 1.panel come with encoder (after bridge remvoed), like that: struct msm_dp_mst_encoder { struct drm_encoder *enc; int stream_id; struct msm_dp_panel *dp_panel; }; 2. During enable and disable, allocate and release dynamically. would you prefer which one? >> >> return rc; >> } >> @@ -882,8 +883,14 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) >> msm_dp_display->aux_base, "dp_aux"); >> msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, >> msm_dp_display->link_base, "dp_link"); >> - msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, >> - msm_dp_display->p0_base, "dp_p0"); >> + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, >> + msm_dp_display->pixel_base[0], "dp_p0"); >> + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, >> + msm_dp_display->pixel_base[1], "dp_p1"); >> + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, >> + msm_dp_display->pixel_base[2], "dp_p2"); >> + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, >> + msm_dp_display->pixel_base[3], "dp_p3"); >> } >> >> void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) >> @@ -1163,6 +1170,7 @@ static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx, size_ >> static int msm_dp_display_get_io(struct msm_dp_display_private *display) >> { >> struct platform_device *pdev = display->msm_dp_display.pdev; >> + int i; >> >> display->ahb_base = msm_dp_ioremap(pdev, 0, &display->ahb_len); >> if (IS_ERR(display->ahb_base)) >> @@ -1192,8 +1200,8 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) >> display->aux_len = DP_DEFAULT_AUX_SIZE; >> display->link_base = display->ahb_base + DP_DEFAULT_LINK_OFFSET; >> display->link_len = DP_DEFAULT_LINK_SIZE; >> - display->p0_base = display->ahb_base + DP_DEFAULT_P0_OFFSET; >> - display->p0_len = DP_DEFAULT_P0_SIZE; >> + display->pixel_base[0] = display->ahb_base + DP_DEFAULT_P0_OFFSET; >> + display->pixel_len = DP_DEFAULT_P0_SIZE; >> >> return 0; >> } >> @@ -1204,10 +1212,20 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) >> return PTR_ERR(display->link_base); >> } >> >> - display->p0_base = msm_dp_ioremap(pdev, 3, &display->p0_len); >> - if (IS_ERR(display->p0_base)) { >> - DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); >> - return PTR_ERR(display->p0_base); >> + display->pixel_base[0] = msm_dp_ioremap(pdev, 3, &display->pixel_len); >> + if (IS_ERR(display->pixel_base[0])) { >> + DRM_ERROR("unable to remap p0 region: %pe\n", display->pixel_base[0]); >> + return PTR_ERR(display->pixel_base[0]); >> + } >> + >> + for (i = DP_STREAM_1; i < display->max_stream; i++) { >> + /* pixels clk reg index start from 3*/ >> + display->pixel_base[i] = msm_dp_ioremap(pdev, i + 3, &display->pixel_len); >> + if (IS_ERR(display->pixel_base[i])) { >> + DRM_DEBUG_DP("unable to remap p%d region: %pe\n", i, >> + display->pixel_base[i]); >> + break; > > No, return an error. > Got it. >> + } >> } >> >> return 0; >