From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4BDAB321434 for ; Wed, 7 Jan 2026 13:16:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767791821; cv=none; b=YyWCeIF22tEmLWtCE7kHo8f+SZxPSKkjMkTijuYptuALJCMAZN8qB7kE2PgIVRszrKfy+hnrVBIIdQbzdhCqI5GN0OHvoVNyvlJquB9bexGjjN9hX4cpaiA7HgD7C+BV5knFAt2JPVwew82H0AL7pKtrUfox+Tl3RuKl4TqituE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767791821; c=relaxed/simple; bh=8XPGWz6gc1WF5JXzink2MSJWua21d/hl8REDDuFkb1I=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rt2WX0WM3oSmgAsaaC5yMokWXRt5FGp+4WrD7d+lKuxAGupKjkKmAMVSJDk04ygfM6Bi4Sq7flEKgPIR03uq6AYhazs47zXtAiFwxGcjSjCT13o3pgRCz2PRfqbJ9pnkiF5kGM6bzFSdw+LW0riVY3VF7kIZ1mtfeyBU5cl3o40= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6C02F497; Wed, 7 Jan 2026 05:16:50 -0800 (PST) Received: from [10.57.48.49] (unknown [10.57.48.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9A0A33F5A1; Wed, 7 Jan 2026 05:16:54 -0800 (PST) Message-ID: <551bb2e3-d7c7-4949-a9bd-ce0cf70e7134@arm.com> Date: Wed, 7 Jan 2026 13:16:52 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/8] dma-mapping: Support batch mode for dma_direct_sync_sg_for_* To: Barry Song <21cnbao@gmail.com> Cc: Leon Romanovsky , catalin.marinas@arm.com, m.szyprowski@samsung.com, will@kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Ada Couprie Diaz , Ard Biesheuvel , Marc Zyngier , Anshuman Khandual , Ryan Roberts , Suren Baghdasaryan , Tangquan Zheng References: <20251226225254.46197-1-21cnbao@gmail.com> <20251226225254.46197-6-21cnbao@gmail.com> <20251227200933.GO11869@unreal> <20251228145041.GS11869@unreal> From: Robin Murphy Content-Language: en-GB In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2026-01-06 7:47 pm, Barry Song wrote: > On Wed, Jan 7, 2026 at 8:12 AM Robin Murphy wrote: >> >> On 2026-01-06 6:41 pm, Barry Song wrote: >>> On Mon, Dec 29, 2025 at 3:50 AM Leon Romanovsky wrote: >>>> >>>> On Sun, Dec 28, 2025 at 09:52:05AM +1300, Barry Song wrote: >>>>> On Sun, Dec 28, 2025 at 9:09 AM Leon Romanovsky wrote: >>>>>> >>>>>> On Sat, Dec 27, 2025 at 11:52:45AM +1300, Barry Song wrote: >>>>>>> From: Barry Song >>>>>>> >>>>>>> Instead of performing a flush per SG entry, issue all cache >>>>>>> operations first and then flush once. This ultimately benefits >>>>>>> __dma_sync_sg_for_cpu() and __dma_sync_sg_for_device(). >>>>>>> >>>>>>> Cc: Leon Romanovsky >>>>>>> Cc: Catalin Marinas >>>>>>> Cc: Will Deacon >>>>>>> Cc: Marek Szyprowski >>>>>>> Cc: Robin Murphy >>>>>>> Cc: Ada Couprie Diaz >>>>>>> Cc: Ard Biesheuvel >>>>>>> Cc: Marc Zyngier >>>>>>> Cc: Anshuman Khandual >>>>>>> Cc: Ryan Roberts >>>>>>> Cc: Suren Baghdasaryan >>>>>>> Cc: Tangquan Zheng >>>>>>> Signed-off-by: Barry Song >>>>>>> --- >>>>>>> kernel/dma/direct.c | 14 +++++++------- >>>>>>> 1 file changed, 7 insertions(+), 7 deletions(-) >>>>>> >>>>>> <...> >>>>>> >>>>>>> - if (!dev_is_dma_coherent(dev)) { >>>>>>> + if (!dev_is_dma_coherent(dev)) >>>>>>> arch_sync_dma_for_device(paddr, sg->length, >>>>>>> dir); >>>>>>> - arch_sync_dma_flush(); >>>>>>> - } >>>>>>> } >>>>>>> + if (!dev_is_dma_coherent(dev)) >>>>>>> + arch_sync_dma_flush(); >>>>>> >>>>>> This patch should be squashed into the previous one. You introduced >>>>>> arch_sync_dma_flush() there, and now you are placing it elsewhere. >>>>> >>>>> Hi Leon, >>>>> >>>>> The previous patch replaces all arch_sync_dma_for_* calls with >>>>> arch_sync_dma_for_* plus arch_sync_dma_flush(), without any >>>>> functional change. The subsequent patches then implement the >>>>> actual batching. I feel this is a better approach for reviewing >>>>> each change independently. Otherwise, the previous patch would >>>>> be too large. >>>> >>>> Don't worry about it. Your patches are small enough. >>> >>> My hardware does not require a bounce buffer, but I am concerned that >>> this patch may be incorrect for systems that do require one. >>> >>> Now it is: >>> >>> void dma_direct_sync_sg_for_cpu(struct device *dev, >>> struct scatterlist *sgl, int nents, enum dma_data_direction dir) >>> { >>> struct scatterlist *sg; >>> int i; >>> >>> for_each_sg(sgl, sg, nents, i) { >>> phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg)); >>> >>> if (!dev_is_dma_coherent(dev)) >>> arch_sync_dma_for_cpu(paddr, sg->length, dir); >>> >>> swiotlb_sync_single_for_cpu(dev, paddr, sg->length, dir); >>> >>> if (dir == DMA_FROM_DEVICE) >>> arch_dma_mark_clean(paddr, sg->length); >>> } >>> >>> if (!dev_is_dma_coherent(dev)) { >>> arch_sync_dma_flush(); >>> arch_sync_dma_for_cpu_all(); >>> } >>> } >>> >>> Should we call swiotlb_sync_single_for_cpu() and >>> arch_dma_mark_clean() after the flush to ensure the CPU sees the >>> latest data and that the memcpy is correct? I mean: >> >> Yes, this and the equivalents in the later patches are broken for all >> the sync_for_cpu and unmap paths which may end up bouncing (beware some >> of them get a bit fiddly) - any cache maintenance *must* be completed >> before calling SWIOTLB. As for mark_clean, IIRC that was an IA-64 thing, >> and appears to be entirely dead now. > > Thanks, Robin. Personally, I would prefer an approach like the one below— > that is, not optimizing the bounce buffer cases, as they are already slow > due to hardware limitations with memcpy, and optimizing them would make > the code quite messy. > > diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c > index 550a1a13148d..a4840f7e8722 100644 > --- a/kernel/dma/direct.c > +++ b/kernel/dma/direct.c > @@ -423,8 +423,11 @@ void dma_direct_sync_sg_for_cpu(struct device *dev, > for_each_sg(sgl, sg, nents, i) { > phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg)); > > - if (!dev_is_dma_coherent(dev)) > + if (!dev_is_dma_coherent(dev)) { > arch_sync_dma_for_cpu(paddr, sg->length, dir); > + if (unlikely(dev->dma_io_tlb_mem)) > + arch_sync_dma_flush(); > + } > > swiotlb_sync_single_for_cpu(dev, paddr, sg->length, dir); > > I’d like to check with you, Leon, and Marek on your views about this. That doesn't work, since dma_io_tlb_mem is always initialised if a SWIOTLB buffer exists at all. Similarly I think the existing dma_need_sync tracking is also too coarse, as that's also always going to be true for a non-coherent device. Really this flush wants to be after the swiotlb_find_pool() check in the swiotlb_tbl_unmap_single()/__swiotlb_sync_single_for_cpu() paths, as that's the only point we know for sure it's definitely needed for the given address. It would then be rather fiddly to avoid potentially-redundant flushes for the non-sg cases (and the final segment of an sg), but as you already mentioned, if it's limited to cases when we *are* already paying the cost of bouncing anyway, perhaps one extra DSB isn't *too* bad if it means zero impact to the non-bouncing paths. Thanks, Robin.