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([2a02:1807:2a00:3400:1b1a:e580:5909:925c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3ecdbc7fe1bsm3414155f8f.52.2025.09.16.23.39.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Sep 2025 23:39:11 -0700 (PDT) Message-ID: <55237b5d-c9b8-4606-8b5d-c7a97218c085@hammernet.be> Date: Wed, 17 Sep 2025 08:39:10 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] riscv: dts: spacemit: add UART pinctrl combinations To: Yixun Lan Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, skhan@linuxfoundation.org, linux-kernel-mentees@lists.linux.dev, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org References: <20250916064739.196695-1-hendrik.hamerlinck@hammernet.be> <20250917012941-GYA1263349@gentoo.org> Content-Language: en-US From: Hendrik Hamerlinck In-Reply-To: <20250917012941-GYA1263349@gentoo.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hello Yixun, On 9/17/25 03:29, Yixun Lan wrote: > Hi Hendrik, > > On 08:47 Tue 16 Sep , Hendrik Hamerlinck wrote: >> Add UART pinctrl configurations based on the SoC datasheet and the >> downstream Bianbu Linux tree. The drive strength values were taken from >> the downstream implementation, which uses medium drive strength. >> CTS/RTS are moved to separate *-cts-rts-cfg states so boards can enable >> hardware flow control conditionally. >> >> Signed-off-by: Hendrik Hamerlinck >> --- >> Changes in v3: >> - Added /omit-if-no-ref/ to pinctrl states to reduce DT size >> >> Changes in v2: >> - Split cts/rts into separate pinctrl configs as suggested >> - Removed options from board DTS files to keep them cleaner >> --- >> arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 432 ++++++++++++++++++- >> 1 file changed, 429 insertions(+), 3 deletions(-) >> >> diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi >> index 381055737422..7811fb485bd4 100644 >> --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi >> +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi >> @@ -11,12 +11,438 @@ >> #define K1_GPIO(x) (x / 32) (x % 32) >> >> &pinctrl { >> + /omit-if-no-ref/ >> + uart0_0_cfg: uart0-0-cfg { >> + uart0-0-pins { >> + pinmux = , /* uart0_txd */ >> + ; /* uart0_rxd */ >> + power-source = <3300>; >> + bias-pull-up; >> + drive-strength = <19>; >> + }; >> + }; >> + >> + /omit-if-no-ref/ >> + uart0_1_cfg: uart0-1-cfg { >> + uart0-1-pins { >> + pinmux = , /* uart0_txd */ >> + ; /* uart0_rxd */ >> + power-source = <3300>; > .. >> + bias-pull-up; > here, see comment below >> + drive-strength = <19>; >> + }; >> + }; >> + >> + /omit-if-no-ref/ >> uart0_2_cfg: uart0-2-cfg { >> uart0-2-pins { >> - pinmux = , >> - ; >> + pinmux = , /* uart0_txd */ >> + ; /* uart0_rxd */ >> + bias-pull-up; >> + drive-strength = <32>; >> + }; >> + }; >> >> - bias-pull-up = <0>; > Sorry, I've overlooked this, the bias-pull-up need to explicitly set to > a vale of 0, 1 - normal pull up, or strong pull up.. for uart, the normal > pull up should be ok > > please refer Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml > > Since the rc6 is already tagged, I'm about to prepare a PR, so If you able > to respin a new version quickly, I'd be happy to take, otherwise let's wait > for next merge window (which shouldn't be a big problem) > > btw, please always do a DT check: > make ARCH=riscv dtbs_check W=1 > Oh, I wasn’t aware of this. I’ll update it accordingly and run the check before sending a new version. Thanks for the advice! Kind regards, Hendrik