From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E95FAB672 for ; Mon, 9 Feb 2026 16:28:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770654483; cv=none; b=i707eME7ApWwNhGje3OYm+tq3rb6CFkdBA+M/mU/Ek+Nz+0LwIiRG5dXkIhxNKMGCWubZa1Qs4G0Ez+nUlVWfqQTftbKmnFwBUX3IIsnmg/MpEp9YnVyZNI+heyZZ+fIKt3hZLZq9PORV8+tuPCujW7NWPhAtEULMrV4l7kmL6Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770654483; c=relaxed/simple; bh=dOoq43Q9E5qzP/zMxM+EwMjwlGRU0elr7efaYZyy53g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UXvjeWBHZQXMyHsrbYUuAZJdfKBK2PsIk8dEJmmVkso1ijuJuY8oDQPs83m1ekVktd8xd/V2GVVBBdM31UGs3u1Ryo/VShMlpBF6YqZJhcH3jGmhhvTaV4PAwEML88TCRL9gX1+kDVbA6+PqTriekSkVdborRlMyhWs5Xl4bOeA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=oYif8k3y; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="oYif8k3y" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=5IZQ4COQKPXn9DHaU1hZteGEj7qfkW1soHzUGkYDH58=; b=oYif8k3yTZnZIcyM4COKRbCgoV W3TYLbDNyqPT1CA6CQ7rIdUQOD7Mvp1SuqLSLkHh62A1fxd8wjYe148jCsoqzpjJPPirB7SZNthL1 lBCUfvEWMN+KtPbK9GGd0SsFQPSFudqZIncwSLImb9CPoLAKwpq5A3yAgAzelBEjwNNmrV5vyt+tC s+sZ+h7CxmAdPaUqmY2zD5bWsHBECk/mmSSA5/1VwLqdJWoEtgIHIacmkWng2QxOmiYuCFPsVfGmz Csp4vG66he2ip+9+C9kYPZPueO34rS5Y1//W7CjpQqHpQyv8WnF4G7RiXWTPssEz6OWRIXcagWOon m/Pe0XBw==; Received: from i53875a32.versanet.de ([83.135.90.50] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vpU78-007nOC-2C; Mon, 09 Feb 2026 17:27:54 +0100 From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= To: Quentin Schulz Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: Re: [PATCH 3/3] arm64: dts: rockchip: add pinctrl for clk-generator GPIO on rk3588-tiger Date: Mon, 09 Feb 2026 17:27:51 +0100 Message-ID: <5539724.6PsWsQAL7t@diego> In-Reply-To: References: <20260205102104.394991-1-heiko@sntech.de> <20260205102104.394991-4-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Donnerstag, 5. Februar 2026, 17:49:15 Mitteleurop=C3=A4ische Normalzeit = schrieb Quentin Schulz: > Hi Heiko, >=20 > On 2/5/26 11:21 AM, Heiko Stuebner wrote: > > From: Heiko Stuebner > >=20 > > While specific driver in the Linux-Kernel handles GPIOs gracefully with= out > > matching pinctrl entries, this might not be true for other operating > > systems. So having pinctrl entries makes the hardware-description > > more complete. > >=20 > > The somewhat similar rk3588-jaguar board has a pinctrl entry already, > > so also add one for rk3588-tiger. > >=20 > > Signed-off-by: Heiko Stuebner > > --- > > arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 8 ++++++++ > > 1 file changed, 8 insertions(+) > >=20 > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm6= 4/boot/dts/rockchip/rk3588-tiger.dtsi > > index 259fb125e13f..91057b166690 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi > > @@ -58,6 +58,8 @@ pcie_refclk: pcie-clock-generator { > > clock-frequency =3D <100000000>; > > clock-output-names =3D "pcie3_refclk"; > > enable-gpios =3D <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKR= EQN_M1_L */ > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&pcie30x4_clkreqn_m1_l>; > > vdd-supply =3D <&vcca_3v3_s0>; > > }; > > =20 > > @@ -357,6 +359,12 @@ module_led_pin: module-led-pin { > > }; > > }; > > =20 > > + pcie30x4 { > > + pcie30x4_clkreqn_m1_l: pcie30x4-clkreqn-m1-l { > > + rockchip,pins =3D <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; >=20 > So this is interesting because it made me double-check the schematics=20 > and I think we did a mistake on Jaguar. >=20 > This one here is fine as this SoC pin is connected to the PDn pin of the= =20 > IC which has an internal Pull-Up, so the state is defined. >=20 > However, on Jaguar this signal controls a transistor and there's no=20 > external Pull-Up or Pull-Down between the SoC and the transistor gate so= =20 > we probably should not have pull_none for the pinconf. The default reset= =20 > state of this pin in Pull-Up so maybe we should go with that such that=20 > there's no difference between the reset default and the time between=20 > application of the pinconf by the core and asserting of the pin by the=20 > driver. What do you think? Looking at the datasheet for the PI6C557-05B, both nPD and OE are described as having an "internal pull up resistor", so the pinconf side should not matter? > As for Tiger, this is fine, so: >=20 > Reviewed-by: Quentin Schulz Heiko