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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amlogic.com; Received: from KL1PR03MB5778.apcprd03.prod.outlook.com (2603:1096:820:6d::13) by SI4PR03MB10101.apcprd03.prod.outlook.com (2603:1096:4:2b2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.15; Wed, 21 Oct 2026 08:24:24 +0000 Received: from KL1PR03MB5778.apcprd03.prod.outlook.com ([fe80::e1e:5c95:a889:828e]) by KL1PR03MB5778.apcprd03.prod.outlook.com ([fe80::e1e:5c95:a889:828e%4]) with mapi id 15.21.0546.012; Wed, 21 Oct 2026 08:24:23 +0000 Message-ID: <55844de7-efa2-42b1-8d5e-94e826ee27fb@amlogic.com> Date: Wed, 21 Oct 2026 16:24:20 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/4] clk: amlogic: Improve the issue of PLL lock failures To: John O'Callaghan Cc: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> <20251031-optimize_pll_driver-v3-2-92f3b2f36a83@amlogic.com> <20261021060005.2947837-1-johnocallaghan@gmail.com> From: Chuan Liu In-Reply-To: <20261021060005.2947837-1-johnocallaghan@gmail.com> Content-Type: text/plain; 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On 10/21/2026 1:59 PM, John O'Callaghan wrote: > [你通常不会收到来自 johnocallaghan@gmail.com 的电子邮件。请访问 https://aka.ms/LearnAboutSenderIdentification，以了解这一点为什么很重要] > > [ EXTERNAL EMAIL ] > > Hi Chuan, > > Jerome asked what was tested; here is a G12A data point. > > On a Radxa Zero (S905Y2, G12A) running v7.3, sys_pll_dco occasionally > fails to lock on cpufreq transitions, at room temperature: > > meson_clk_pll_set_rate: pll sys_pll_dco didn't lock, trying to set old rate 6000000000 > > It happens with all the sys_pll OPPs (old DCO rates 3216, 3408, 3600, > 4800, 5592 and 6000 MHz) but, here, only while the video decoder is > busy. I understand there should be no direct connection between the video decoder and sys_pll lock failure. Perhaps it's due to increased power consumption when the video decoder is active, causing higher power supply ripple? Have you conducted comparative tests on the ripple conditions of various power rails after enabling the video decoder, especially VDDAO_1V8 (which supplies power to the PLL)? The operation of the video decoder may also cause more frequent load changes, leading the sys_pll to re-lock frequently and thus increasing the probability of PLL lock failure. Reproducer: the userspace governor, random writes of the > 1200-1800 MHz OPPs to scaling_setspeed (~700 transitions/s), with a > GStreamer v4l2 decode loop (meson vdec, H.264 + VP9 1080p) running > alongside. 46 C SoC temperature. Previously, we encountered similar PLL lock failure issues during low-temperature burn-in testing (at -10°C to -15°C) with G12A, and we had previously pushed a mandatory patch to customers. This patch significantly improves PLL lock failure scenarios, you can first apply it locally. > > transitions lock failures > v7.3 500290 33 > v7.3, no decoder running 250056 0 > v7.3 + this series (1-4) 500089 0 > v7.3 + patch 2/4 only 500066 0 > > So on G12A it is the 20 us delays of this patch that make the > difference. > > Tested-by: John O'Callaghan # Radxa Zero (G12A) Thanks! > > The testing was scripted with the help of an LLM coding assistant; I > ran it on my board and checked the results. > > Thanks, > John -- Best regards, Chuan