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Wed, 21 May 2025 21:41:00 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54LLexa5024405 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 May 2025 21:40:59 GMT Received: from [10.216.45.12] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 21 May 2025 14:40:53 -0700 Message-ID: <5584c019-d435-4d1b-b38c-80fb9b9f00f6@quicinc.com> Date: Thu, 22 May 2025 03:10:48 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V5 09/11] scsi: ufs: qcom : Refactor phy_power_on/off calls To: Manivannan Sadhasivam CC: , , , , , , , , , , , , , , References: <20250515162722.6933-1-quic_nitirawa@quicinc.com> <20250515162722.6933-10-quic_nitirawa@quicinc.com> Content-Language: en-US From: Nitin Rawat In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: vps-OOowh3yznaNn_750c9vFtF-5w0f2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIxMDIxNSBTYWx0ZWRfX26+UD3SP4Ydg q4qpi+OgcG6HdDHPrRQglHuJEbfb+ucJxnjt1c/hu3WQjoyXWpFVrNDe+4NDnOI993YwbsHYOWE io+KfWEpg82wU9w0Y1XRgX3IRkwJO9Gf9LQRDuzqUHlNh/h/90W2hkt3TGfkkEM0MOAYOU+dmik sAQOhinvdur8dgRlWBtAT7Mp8dmCJ511txZHdJZVCLjK8c3YEZ1jzVuegLyzmvgPBT4DPlaZ8eN zEJg9M7coXNnkm3EqUOrPcXKrrw0bnZ1DTdh2572vP75FfhzXX0Aa/RdWmIGnGuty2WOCHDogjL D5IiyxjVKmSNkN+qwURSGHuD6OTdIZYsF0sFEDcrejBsFE1h/Jm095UEDLE4Nn71ELEA53HN1hI 5d4g3aS2DacpJ9huwxV7D2Aqvqe5Ajlq755gaW0bq8Sf0m0hP8tIYH0Wi5l+voT0YzURgF0Z X-Authority-Analysis: v=2.4 cv=fZOty1QF c=1 sm=1 tr=0 ts=682e486c cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=NAncGNguUiBsChi5r5oA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: vps-OOowh3yznaNn_750c9vFtF-5w0f2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-21_07,2025-05-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 adultscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505210215 On 5/21/2025 7:27 PM, Manivannan Sadhasivam wrote: > On Thu, May 15, 2025 at 09:57:20PM +0530, Nitin Rawat wrote: >> Commit 3f6d1767b1a0 ("phy: ufs-qcom: Refactor all init steps into >> phy_poweron") removes the phy_power_on/off from ufs_qcom_setup_clocks > > s/removes/moved Sure, will address in next patchset. > >> to suspend/resume func. >> >> To have a better power saving, remove the phy_power_on/off calls from >> resume/suspend path and put them back to ufs_qcom_setup_clocks, so that >> PHY regulators & clks can be turned on/off along with UFS's clocks. >> >> Since phy phy_power_on is separated out from phy calibrate, make >> separate calls to phy_power_on and phy_calibrate calls from ufs qcom >> driver. >> > > This patch is not calling phy_calibrate(). updated commit text to remove phy_Calibrate from commit text > >> Co-developed-by: Can Guo >> Signed-off-by: Can Guo >> Signed-off-by: Nitin Rawat >> --- >> drivers/ufs/host/ufs-qcom.c | 61 ++++++++++++++++++------------------- >> 1 file changed, 29 insertions(+), 32 deletions(-) >> > > [...] > >> static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, >> enum ufs_notify_change_status status) >> { >> struct ufs_qcom_host *host = ufshcd_get_variant(hba); >> + struct phy *phy = host->generic_phy; >> + int err; >> >> /* >> * In case ufs_qcom_init() is not yet done, simply ignore. >> @@ -1157,10 +1141,22 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, >> /* disable device ref_clk */ >> ufs_qcom_dev_ref_clk_ctrl(host, false); >> } >> + >> + err = phy_power_off(phy); >> + if (err) { >> + dev_err(hba->dev, "phy power off failed, ret=%d\n", err); >> + return err; >> + } >> } >> break; >> case POST_CHANGE: >> if (on) { >> + err = phy_power_on(phy); >> + if (err) { >> + dev_err(hba->dev, "phy power on failed, ret = %d\n", err); >> + return err; >> + } >> + >> /* enable the device ref clock for HS mode*/ >> if (ufshcd_is_hs_mode(&hba->pwr_info)) >> ufs_qcom_dev_ref_clk_ctrl(host, true); >> @@ -1343,9 +1339,10 @@ static int ufs_qcom_init(struct ufs_hba *hba) >> static void ufs_qcom_exit(struct ufs_hba *hba) >> { >> struct ufs_qcom_host *host = ufshcd_get_variant(hba); >> + struct phy *phy = host->generic_phy; >> >> ufs_qcom_disable_lane_clks(host); >> - phy_power_off(host->generic_phy); >> + phy_power_off(phy); > > This change is not at all needed. In the current code, PHY resources (clocks and rails) remain active even when the link is in a hibernate state and all controller clocks are off. This results in a significant power penalty and can prevent CX power collapse. These rails and clocks are only turned off when a system suspend is triggered, and even then, only at SPM level 5 where the link is turned off. This approach is not power-efficient. As part of this series, the code that enables/disables the PHY's regulators and clocks is now confined to the phy_power_on and phy_power_off calls, with the rest moved to the calibration phase. Therefore, we are invoking the phy_power_off and phy_power_on calls from ufs_qcom_setup_clocks, ensuring that the PHY's regulators and clocks can be turned on/off along with the UFS clocks, thereby achieving power savings. Therefore, this patch is the cornerstone of this series. Regards, Nitin > > - Mani >