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Fri, 29 Aug 2025 01:24:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHBH0NFwkkluNtoyFp/sOGVeW9GAErFZVXGcvAduDHifrpu0UX3YiAiOgtNINcHVTBJqK21Bw== X-Received: by 2002:a17:903:384f:b0:246:2b29:71c7 with SMTP id d9443c01a7336-2462ee92ef2mr364175035ad.25.1756455890943; Fri, 29 Aug 2025 01:24:50 -0700 (PDT) Received: from [192.168.0.195] ([49.204.25.176]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-24905da4d44sm17598275ad.83.2025.08.29.01.24.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Aug 2025 01:24:50 -0700 (PDT) Message-ID: <558ca51d-e1ca-4267-9166-2b929216c43a@oss.qualcomm.com> Date: Fri, 29 Aug 2025 13:54:45 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250829-glymur-disp-clock-controllers-v1-0-0ce6fabd837c@oss.qualcomm.com> <20250829-glymur-disp-clock-controllers-v1-1-0ce6fabd837c@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Z/vsHGRA c=1 sm=1 tr=0 ts=68b163d4 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ubyLEIH+BItvSySilgXupg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=1ut_qpqdL47trf14q9UA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfXwF/y4n767fiT TdNjley/SKp8EYHk3tAAKr8IiiDG7tyHYf7A3fMXAZeRoYIE+5yS5hHg2q64KOSYv26dt7SpWwm yqnEsLJ6y3+6Y6ClKg6/TqRF3RLLrCXOz41ougdHFwm98p+9mwhTnbquxEBLcXRmvqnvHmZjg2h f4A0g5xEj2aC/UpaUaUMKmrSJKaaBJKtDu5OB39pITGn7AK4zffO55DJ1mHRedQIpnEgmV6UF36 RplSqIW89p/2StA1oRP+kJAxB0wY1lyHMQikgy/9PmzPHVZq1VRQq95aUI9xjejNb81WbnUeCJ2 8RVdHrTWdWUDY5exbl3j6IbvYdZ5Yn3lsQn4OETSvrGJrjZezmr7WAhZUmkOo6/QkujORRONevp fueIMubf X-Proofpoint-GUID: 6tfLnSBY6atYMDKxgxrmVpqVh5J4p8_Z X-Proofpoint-ORIG-GUID: 6tfLnSBY6atYMDKxgxrmVpqVh5J4p8_Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-29_02,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 suspectscore=0 impostorscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 On 8/29/2025 1:42 PM, Dmitry Baryshkov wrote: > On Fri, Aug 29, 2025 at 01:28:03PM +0530, Taniya Das wrote: >> Add the device tree bindings for the display clock controller which are >> required on Qualcomm Glymur SoC. >> >> Signed-off-by: Taniya Das >> --- >> .../bindings/clock/qcom,glymur-dispcc.yaml | 99 ++++++++++++++++++ >> include/dt-bindings/clock/qcom,glymur-dispcc.h | 114 +++++++++++++++++++++ >> 2 files changed, 213 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..063da2416dbaed764b8579a090bc5fc0531ab60d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml >> @@ -0,0 +1,99 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Display Clock & Reset Controller on GLYMUR >> + >> +maintainers: >> + - Taniya Das >> + >> +description: | >> + Qualcomm display clock control module which supports the clocks, resets and >> + power domains for the MDSS instances on GLYMUR SoC. >> + >> + See also: >> + include/dt-bindings/clock/qcom,dispcc-glymur.h >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,glymur-dispcc >> + >> + clocks: >> + items: >> + - description: Board CXO clock >> + - description: Board sleep clock >> + - description: DisplayPort 0 link clock >> + - description: DisplayPort 0 VCO div clock >> + - description: DisplayPort 1 link clock >> + - description: DisplayPort 1 VCO div clock >> + - description: DisplayPort 2 link clock >> + - description: DisplayPort 2 VCO div clock >> + - description: DisplayPort 3 link clock >> + - description: DisplayPort 3 VCO div clock >> + - description: DSI 0 PLL byte clock >> + - description: DSI 0 PLL DSI clock >> + - description: DSI 1 PLL byte clock >> + - description: DSI 1 PLL DSI clock >> + - description: Standalone PHY 0 PLL link clock >> + - description: Standalone PHY 0 VCO div clock >> + - description: Standalone PHY 1 PLL link clock >> + - description: Standalone PHY 1 VCO div clock >> + >> + power-domains: >> + description: >> + A phandle and PM domain specifier for the MMCX power domain. >> + maxItems: 1 >> + >> + required-opps: >> + description: >> + A phandle to an OPP node describing required MMCX performance point. >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - clocks >> + - power-domains >> + - '#power-domain-cells' >> + >> +allOf: >> + - $ref: qcom,gcc.yaml# >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include > Should not be needed Sure Dmitry, will remove this in the next patchset. -- Thanks, Taniya Das