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Tue, 01 Sep 2026 02:48:10 -0700 (PDT) X-Received: by 2002:a05:620a:1989:b0:939:4a24:4de4 with SMTP id af79cd13be357-9394a244ecemr463031785a.5.1788256089635; Tue, 01 Sep 2026 02:48:09 -0700 (PDT) Received: from [192.168.202.12] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255ee0b330sm547429266b.1.2026.09.01.02.48.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Sep 2026 02:48:08 -0700 (PDT) Message-ID: <558d9ec7-e5dc-4257-9ef4-c0433a4177c2@oss.qualcomm.com> Date: Tue, 1 Sep 2026 11:48:06 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functions To: Shawn Guo , Bartosz Golaszewski Cc: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260830030201.135637-1-shengchao.guo@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260830030201.135637-1-shengchao.guo@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: lW08ufnxyjyMHOI1iRLc7w-eNMhUjHBm X-Authority-Analysis: v=2.4 cv=G9Ms1dk5 c=1 sm=1 tr=0 ts=6a969f5b cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=2HO_7AbmPCLmE9qJQqQA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: lW08ufnxyjyMHOI1iRLc7w-eNMhUjHBm X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NiBTYWx0ZWRfX5llNsPyHf5b7 YwwZYBMCe/xYRqYuX7y8bfv6dVw2dX8Y2jnATXXn1LFc+0QRhvgM5doPEqYDn6XRz2zx7ooqqMd fu8De3dmEBneO2+Wbp3YHQ30OVUWvjY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NiBTYWx0ZWRfX7aBSaSDyLjkW MkT7dvVvl2r24CvNakYDVXOpYSz5HsF6/gOAMkK5hvfBn0r9obPS4cR0Na3MrQlENZFr4SFA3LE smj7lO34/HssZ0UyElrwBF8IzY3dGrsNzahENPfVtMjMTtE6uipfYEKEWYFK0SFFF0EPBjpekUJ HIOeznKcLDSGOnnvK3g8QaEv+fTFHK9o1p3iI54aV6xQARsrzH61CC/0rsfB2QeMmlwhRBlv+7a 20ocnUy6EPTOpqg74iGJ4MsmpwpnwnWvSiK4H0otwdvQ1AfVd6/WM9DWfGZnW44VUyISONB7QCA cou92gXXCe1am2DEpt4ueT9eDKlm/+to0qD8PrvsWfLt1Su7DzIdgU7nPQYuDR1S5nell1QE58s OoqiVJKRLUSQN40u84Alv7z5T5za9jp2dm+gO5c2VZvHqYkT8IP0wBRTTejTSQtBI+bdUxatTn4 6MvpsYM950j0J1dvAsg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 impostorscore=0 spamscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010086 On 8/30/26 5:02 AM, Shawn Guo wrote: > QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two > pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART > TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 > respectively. > > Both mux values were named "qup1_se2" (respectively "qup1_se3"), so the > two distinct lane pairs became indistinguishable. msm_pinmux_set_mux() > stops at the first entry matching the requested function, which means > mux value 1 was always selected and the I2C lanes could never be muxed > out. In practice i2c9 and i2c10 got the UART lanes and did not work, > while uart9 and uart10 happened to be muxed correctly. > > Give each lane pair its own function, following the _01/_23 naming > already used for the same hardware arrangement by the shikra, eliza, > hawi and maili TLMM drivers. Both functions still cover the full pin > pair, so a single pinctrl state per protocol remains sufficient. > > Drop gpio129/gpio130 from the SE2 group list, since those pins > belong to SE3 and were never reachable through the SE2 function. > > Also rename QUP1 SE2/SE3 functions in the binding doc accordingly. > > While at it, add missing "gpio", "qup3_se0_mira" and "qup3_se0_mirb" > to the binding function enum to get the list complete. > > Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") > Cc: stable@vger.kernel.org > Assisted-by: LLM > Signed-off-by: Shawn Guo > --- Reviewed-by: Konrad Dybcio Konrad