From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753917AbbGBABw (ORCPT ); Wed, 1 Jul 2015 20:01:52 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:57254 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753382AbbGBABn (ORCPT ); Wed, 1 Jul 2015 20:01:43 -0400 X-AuditID: cbfec7f4-f79c56d0000012ee-f0-55947f641fe4 Message-id: <55947F65.8010404@samsung.com> Date: Thu, 02 Jul 2015 09:01:41 +0900 From: Krzysztof Kozlowski User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-version: 1.0 To: Chanwoo Choi , s.nawrocki@samsung.com, tomasz.figa@gmail.com, mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org Cc: thomas.ab@samsung.com, b.zolnierkie@samsung.com, kyungmin.park@samsung.com, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v5 2/3] ARM: dts: Add CPU OPP and regulator supply property for Exynos3250 References: <1435756877-26736-1-git-send-email-cw00.choi@samsung.com> <1435756877-26736-3-git-send-email-cw00.choi@samsung.com> In-reply-to: <1435756877-26736-3-git-send-email-cw00.choi@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42I5/e/4Fd2U+imhBr0zNC02zljPanH9y3NW i/lHzrFavH5haNH/+DWzxdmmN+wWmx5fY7X42HOP1eLyrjlsFjPO72OyuHjK1eLwm3ZWix9n ulksOpYxWqza9YfRgd/j/Y1Wdo/Lfb1MHjtn3WX32LSqk81j85J6j74tqxg9Pm+SC2CP4rJJ Sc3JLEst0rdL4Mq4cGYzc8FDoYqVx5tYGxhf83UxcnJICJhIXLi2nAnCFpO4cG89WxcjF4eQ wFJGicMrNzNBOE8ZJXYd/swOUsUroCUx9cRtNhCbRUBV4tncBrA4m4CxxOblS8DiogIREm8v n2SCqBeU+DH5HgvIIBGBOYwSvdemgjnMAp+AnC2dLCBVwgIJEjMPtbJDrGtklDh1+ynYKE4B N4mnG3pZuxg5gDr0JO5f1AIJMwvIS2xe85Z5AqPALCRLZiFUzUJStYCReRWjaGppckFxUnqu oV5xYm5xaV66XnJ+7iZGSBR92cG4+JjVIUYBDkYlHt4VNVNChVgTy4orcw8xSnAwK4nwXgkC CvGmJFZWpRblxxeV5qQWH2KU5mBREuedu+t9iJBAemJJanZqakFqEUyWiYNTqoExal6j5X7/ zf8339mYcqeIN1clwujPa2bxSP13rR9uGd6+6Kt5O/Xl5vhD2UEhEW0NHEwZXfG/7oYGN4Wm T/taflos+fFr/sgN8c96P5eurCs7dUaS/w/LswesLTxfNm6deFZwiq1zR+jKR+UKJ2zfVH98 8cx+btamlLxLSTXBkb+CbJgzqsKVWIozEg21mIuKEwG3WHjDngIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01.07.2015 22:21, Chanwoo Choi wrote: > This patch add CPU operating points which include CPU frequency and regulator > voltage to use generic cpufreq drivers. > > Cc: Kukjin Kim > Cc: Krzysztof Kozlowski > Signed-off-by: Chanwoo Choi > Acked-by: Kyungmin Park > --- > arch/arm/boot/dts/exynos3250-monk.dts | 4 ++++ > arch/arm/boot/dts/exynos3250-rinato.dts | 4 ++++ > arch/arm/boot/dts/exynos3250.dtsi | 15 +++++++++++++++ > 3 files changed, 23 insertions(+) The patch looks good. Could you put the 'cpu' nodes in alphabetical order? The order for Rinato board is already broken but still putting it after 'adc' node would be better. With the change above: Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof > > diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts > index a5863acc5fff..fc6604d68864 100644 > --- a/arch/arm/boot/dts/exynos3250-monk.dts > +++ b/arch/arm/boot/dts/exynos3250-monk.dts > @@ -118,6 +118,10 @@ > }; > }; > > +&cpu0 { > + cpu0-supply = <&buck2_reg>; > +}; > + > &adc { > vdd-supply = <&ldo3_reg>; > status = "okay"; > diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts > index 031853b75528..c8a083b376c9 100644 > --- a/arch/arm/boot/dts/exynos3250-rinato.dts > +++ b/arch/arm/boot/dts/exynos3250-rinato.dts > @@ -109,6 +109,10 @@ > }; > }; > > +&cpu0 { > + cpu0-supply = <&buck2_reg>; > +}; > + > &adc { > vdd-supply = <&ldo3_reg>; > status = "okay"; > diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi > index d7201333e3bc..e0f3b2ed41a3 100644 > --- a/arch/arm/boot/dts/exynos3250.dtsi > +++ b/arch/arm/boot/dts/exynos3250.dtsi > @@ -53,6 +53,21 @@ > compatible = "arm,cortex-a7"; > reg = <0>; > clock-frequency = <1000000000>; > + clocks = <&cmu CLK_ARM_CLK>; > + clock-names = "cpu"; > + > + operating-points = < > + 1000000 1150000 > + 900000 1112500 > + 800000 1075000 > + 700000 1037500 > + 600000 1000000 > + 500000 962500 > + 400000 925000 > + 300000 887500 > + 200000 850000 > + 100000 850000 > + >; > }; > > cpu1: cpu@1 { >