Re: [PATCH v2 3/7] clk: renesas: r8a779g0: Add display related clocks

[Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>]

Hi Geert, Laurent,

On 30/11/2022 21:18, Geert Uytterhoeven wrote:
> Hi Tomi,
> 
> On Wed, Nov 23, 2022 at 8:00 AM Tomi Valkeinen
> <tomi.valkeinen+renesas@ideasonboard.com> wrote:
>> Add clocks related to display which are needed to get the DSI output
>> working.
>>
>> Extracted from Renesas BSP tree.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
>> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> 
> Thanks for your patch!
> 
>> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
>> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
>> @@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
>>          DEF_FIXED("viobusd2",   R8A779G0_CLK_VIOBUSD2,  CLK_VIO,        2, 1),
>>          DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
>>          DEF_FIXED("vcbusd2",    R8A779G0_CLK_VCBUSD2,   CLK_VC,         2, 1),
>> +       DEF_FIXED("dsiref",     R8A779G0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
>> +       DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  0x884),
>>
>>          DEF_GEN4_SDH("sd0h",    R8A779G0_CLK_SD0H,      CLK_SDSRC,         0x870),
>>          DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       R8A779G0_CLK_SD0H, 0x870),
>> @@ -161,6 +163,14 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
>>          DEF_MOD("avb0",         211,    R8A779G0_CLK_S0D4_HSC),
>>          DEF_MOD("avb1",         212,    R8A779G0_CLK_S0D4_HSC),
>>          DEF_MOD("avb2",         213,    R8A779G0_CLK_S0D4_HSC),
>> +
> 
> Weird horizontal and vertical spacing below...
> 
>> +       DEF_MOD("dis0",                 411,    R8A779G0_CLK_S0D3),
> 
> I doubt this parent clock is correct.
> Based on Table 8.1.4e ("Lists of CPG clocks generated from PLL5"),
> this should be one of the VIOBUS clocks.
> VIOBUSD2 has the same rate as S0D3, so I'd use that one.
> 
>> +       DEF_MOD("dsitxlink0",           415,    R8A779G0_CLK_DSIREF),
>> +       DEF_MOD("dsitxlink1",           416,    R8A779G0_CLK_DSIREF),

Now that you started questioning about the clocks, I started to wonder 
about the DSI clocks. They don't quite make sense to me, but here also I 
just assumed it's "fine" as I copied it and it works.

The VIOBUS & VIOBUSD2 are marked to as going to the DSI. But we don't 
actually mark any of the DSI clocks as coming from those sources.

DSIREF is quite clear, it's the source for DSI PLL.

DSIEXT goes to the DSI PHY and is also marked to be used for LP-TX.

In the DT we have now:

clocks = <&cpg CPG_MOD 415>,
	 <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
	 <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
clock-names = "fck", "dsi", "pll";

The "dsi" clock name is a bit vague, but maybe it's "not fclk, not pll, 
but still needed for dsi"? =)

Is it ok to refer to DSIEXT & DSIREF like that, or should they be in the 
r8a779g0_mod_clks list? Or is that list for fclks only?

So the fclk in the dts is mod clock 415 (416 for the second dsi), which 
is dsitxlink0 or dsitxlink1. Well, those names don't quite make sense if 
it's a fclk.

I would rename those clocks to "dsi0" and "dsi1", and source them from 
R8A779G0_CLK_VIOBUSD2, similarly to the other video clocks.

Does the above make sense?

  Tomi