From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753133AbbGMKFM (ORCPT ); Mon, 13 Jul 2015 06:05:12 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:40140 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751530AbbGMKFH (ORCPT ); Mon, 13 Jul 2015 06:05:07 -0400 Message-ID: <55A38D2E.9010500@ti.com> Date: Mon, 13 Jul 2015 13:04:30 +0300 From: Roger Quadros User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Tony Lindgren CC: , , , , , , , Subject: Re: [PATCH 03/12] mtd: nand: omap: Move IRQ handling from GPMC to NAND driver References: <1436531019-18088-1-git-send-email-rogerq@ti.com> <1436531019-18088-4-git-send-email-rogerq@ti.com> <20150713071008.GC26485@atomide.com> In-Reply-To: <20150713071008.GC26485@atomide.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tony, On 13/07/15 10:10, Tony Lindgren wrote: > * Roger Quadros [150710 05:26]: >> Since the Interrupt Events are used only by the NAND driver, >> there is no point in managing the Interrupt registers >> in the GPMC driver and complicating it with irqchip modeling. > > I don't think it's a good idea to allow external drivers to > tinker directly with GPMC registers. How about just set up GPMC > as an irqchip for the edge detection interrupts? > > I think we already have devices with multiple NAND chips. And > there's nothing stopping other drivers from using the edge > detection interrupts. OK. The GPMC_IRQ registers manage 2 NAND specific interrupts (terminalcount and fifo) and 'n' WAIT pin edge interrupts. So we can model this as a irqchip with 'n + 2' interrupts. We need to take care that if a GPMC chip select needs a wait pin then it can't be used as a generic interrupt. We need to get rid of omap_dev_ready() in nand/omap2.c as it accesses the GPMC_STATUS register directly. Plus it is hard coded to only monitor wait0 pin. What is the best map we should use for irqchip? Some Socs have 4 WAIT pins, some have 3 and some have 2. Should we start with 0,1,2, for the wait pins and use the next available free one for the NAND? cheers, -roger