From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753463AbbISBAj (ORCPT ); Fri, 18 Sep 2015 21:00:39 -0400 Received: from mail-by2on0056.outbound.protection.outlook.com ([207.46.100.56]:48886 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751310AbbISBAi (ORCPT ); Fri, 18 Sep 2015 21:00:38 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=David.Daney@caviumnetworks.com; Subject: Re: [PATCH 2/3] PCI: Add quirks for devices found on Cavium ThunderX SoCs. To: Arnd Bergmann References: <1442529694-1792-1-git-send-email-ddaney.cavm@gmail.com> <3066583.BWDZlYWxXU@wuerfel> <55FC4330.10302@caviumnetworks.com> <2512701.zkjk3n3AQS@wuerfel> CC: , David Daney , , Bjorn Helgaas , , Will Deacon , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , , Marc Zyngier , David Daney From: David Daney Message-ID: <55FCB3AC.8080709@caviumnetworks.com> Date: Fri, 18 Sep 2015 18:00:28 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <2512701.zkjk3n3AQS@wuerfel> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.194] X-ClientProxiedBy: SN1PR0701CA0063.namprd07.prod.outlook.com (25.163.126.31) To BN3PR0701MB1717.namprd07.prod.outlook.com (25.163.39.16) X-Microsoft-Exchange-Diagnostics: 1;BN3PR0701MB1717;2:PYNEtRIkeSbLBgjDmmrFikYdz9zBK3kpRV6YqBP3kOoyaGcal9+0Yn3/727GK3wWp5/rfYlXxUCpcomLCCow9dtLWn0PcnyiaCk9dyGRPcaGbMVDmDrecthj5qW5YJwoZe4HGGBoA4cdszkaYl+oAvYVW/Ilzui/jDM9CuG3BXk=;3:1fbkJrT9JQX9fiCQcD1cbp/0IjT3jeB9KumEWZy74S6zY+NkbhMlFzYGPh6rtLA5/+HN+PtuJbX2kZqgINP2yb6FWgMFAgPYzAovqxhBJ1Fn+A19/e/cs/AEdSg1/n2F29vNDlh2okmNT+8+AbzlFg==;25:93fS5jd+4aQrhdUkQ9ja5AX7A621fdlhv9Xkjp0oZebUb2NIh2X2v18dEuY0mrdObUSET7aZzvnNTvOLjad30JUJBNf1zWO5oJb1kR26EHUwn3ZaaK6Cjmz7bojmjR43LEnmuJ9/Tbopn7vczn6psmnSDVzse38PbLM2c6FO+RNIrXTqmPSqZNLL0jGLfb8MZTv1HJJ+hA26IOoI+F1/ILsw6z2q9vsofn+e4L230ARbEAEEImj4Ik5R6KwxPoTzQrAO7QK8BXQKH2gixJBumg== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR0701MB1717; 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So, fix them up. >>>> >>>> Signed-off-by: David Daney >>>> >>> >>> You should be able to just mark the BARs as fixed in DT I think we can switch to PCI_PROBE_ONLY, and have all non-fixed BAR devices configured by firmware. This may significantly simplify any quirks required in the kernel. >> >> In the case of ACPI, there is no DT. So we would need a different >> solution for ACPI. What would you recommend for ACPI? > > I would expect that this does not matter at all on ACPI, because > the devices that need it are not hot-plugged, and all boot-time > devices are probed by the firmware: the ACPI PCI implementation > does not reassign any BARs, except for the hotplug case. > >> Also, can you point me to the OF device tree specification where it >> tells how to specify PCI BAR addresses, I would especially be interested >> in knowing how to specify fixed SRIOV BAR addresses in the device tree. > > This is the 'n' bit mentioned sections 2.1.3 and 2.2.1.1 of the > PCI binding. When it is set, the OS is not supposed to try to > reassign the BAR even on machines that otherwise do a complete > rescan. > > The PCI binding traditionally requires you to list all PCI devices > in DT, Linux as an extension (for the flattened DT format) allows > leaving out the devices, but in this case you probably need to > list every device that has a fixed BAR. > >> Yes, it is a bit of a hack. That is why I put it in its own file, and >> only try to hack up PCI devices that exactly match the vendor and device >> ids that need fixing. >> >> IMHO, putting infrastructure into drivers/pci/probe.c, et al. to handle >> this would be much more intrusive. > > My guess is that it's already there, but even if it's not, this is a > generic well-defined case that has a standardized binding, and we should > implement that. > >> For the record: The PCI Enhanced Allocation (EA) capability (approved >> by PCI SIG on 23 October 2014) is the proper way to handle this going >> forward. However, this is not yet implemented in the SoCs that this >> patch addresses. Our plan is to implement the EA capability in the core >> PCI code, so that we do not need to keep adding devices to this fixup code. > > Good, but still this should only be required for the embedded case where > you don't have a firmware to probe the bus. > > Arnd >