From: "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de,
mingo@redhat.com
Subject: Re: [PATCH] x86/CPU/AMD: Fix LLC ID bit-shift calculation
Date: Mon, 18 Jun 2018 13:46:11 -0500 [thread overview]
Message-ID: <55a20153-9416-404b-7442-ed851386e2e0@amd.com> (raw)
In-Reply-To: <20180618182315.GE24921@zn.tnic>
Boris,
On 6/18/2018 1:23 PM, Borislav Petkov wrote:
> On Mon, Jun 18, 2018 at 01:14:11PM -0500, Suthikulpanit, Suravee wrote:
>> This enumeration is only for the family17h model 00-1Fh of hardware
>> revision. The patch is intended for the future revision of hardware.
>
> I realized that but the same holds true for the future revision - there
> you need to remove thread ID and core ID too, right?
>
Your understanding is correct. I was not sure about what you were
referring to earlier. Basically, the number of threads sharing cache is
used to calculate the amount of right-shifting of APIC ID, which results
in removing the core and thread ID bits.
Suravee
next prev parent reply other threads:[~2018-06-18 18:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-13 18:43 Suravee Suthikulpanit
2018-06-18 17:20 ` Borislav Petkov
2018-06-18 18:14 ` Suthikulpanit, Suravee
2018-06-18 18:23 ` Borislav Petkov
2018-06-18 18:46 ` Suthikulpanit, Suravee [this message]
2018-06-18 18:57 ` Borislav Petkov
2018-06-22 19:24 ` [tip:x86/urgent] " tip-bot for Suravee Suthikulpanit
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