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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5bfe0747766sm515667e87.69.2026.10.31.04.46.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 31 Oct 2026 04:46:54 -0700 (PDT) Message-ID: <55aef663-254a-4d36-b9ec-3ce7f4c4c74a@linaro.org> Date: Sat, 31 Oct 2026 13:46:53 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v23 12/15] arm64: dts: qcom: kaanapali: Add CAMSS and CSIPHY block definitions To: Hangxiang Ma , Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Konrad Dybcio References: <20261028-kaanapali-camss-v23-0-95f250b18612@oss.qualcomm.com> <20261028-kaanapali-camss-v23-12-95f250b18612@oss.qualcomm.com> From: Vladimir Zapolskiy In-Reply-To: <20261028-kaanapali-camss-v23-12-95f250b18612@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/28/26 17:20, Hangxiang Ma wrote: > Describe the CAMSS and CSIPHY blocks on Kaanapali so that camera pipelines > can be enabled by board device trees. > > The camera subsystem contains: > - 6 x CSIPHY (CSI Physical Layer) > - 3 x TPG (Test Pattern Generator) > - 3 x CSID (CSI Decoder) > - 2 x CSID Lite > - 3 x VFE (Video Front End), 5 RDI per VFE > - 2 x VFE Lite, 4 RDI per VFE Lite > > Reviewed-by: Konrad Dybcio > Signed-off-by: Hangxiang Ma > --- > arch/arm64/boot/dts/qcom/kaanapali.dtsi | 401 ++++++++++++++++++++++++++++++++ > 1 file changed, 401 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi > index e48a179d0722..0c8fd7da55b7 100644 > --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi > +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi > @@ -20,6 +20,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -3597,6 +3598,384 @@ usb_dp_qmpphy_dp_in: endpoint { > }; > }; > > + camss: isp@900b000 { > + compatible = "qcom,kaanapali-camss"; > + > + reg = <0x0 0x0900b000 0x0 0x1000>, > + <0x0 0x09253000 0x0 0x5e80>, > + <0x0 0x09263000 0x0 0x5e80>, > + <0x0 0x09273000 0x0 0x5e80>, > + <0x0 0x092d3000 0x0 0x3880>, > + <0x0 0x092e7000 0x0 0x3880>, > + <0x0 0x093fd000 0x0 0x400>, > + <0x0 0x093fe000 0x0 0x400>, > + <0x0 0x093ff000 0x0 0x400>, > + <0x0 0x09151000 0x0 0x20000>, > + <0x0 0x09171000 0x0 0x20000>, > + <0x0 0x09191000 0x0 0x20000>, > + <0x0 0x092dc000 0x0 0x1300>, > + <0x0 0x092f0000 0x0 0x1300>; > + reg-names = "top", > + "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csitpg0", > + "csitpg1", > + "csitpg2", These I/O regions should be named "tpgX". > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, > + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, > + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, > + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, > + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, > + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, > + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, > + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_TFE_0_MAIN_CLK>, > + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, > + <&camcc CAM_CC_TFE_1_MAIN_CLK>, > + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, > + <&camcc CAM_CC_TFE_2_MAIN_CLK>, > + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, > + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; > + clock-names = "camnoc_nrt_axi", > + "camnoc_rt_axi", > + "cpas_ahb", > + "cpas_fast_ahb", > + "cpas_vfe0", > + "cpas_vfe1", > + "cpas_vfe2", > + "cpas_vfe_lite", > + "csid", > + "csid_csiphy_rx", This clock should be named "csiphy_rx" like on sa8775p and a number of other platforms. > + "gcc_axi_hf", > + "gcc_axi_sf", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe1", > + "vfe1_fast_ahb", > + "vfe2", > + "vfe2_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid", > + "qdss_debug_xo"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "ahb", > + "hf_mnoc"; > + > + iommus = <&apps_smmu 0x1c00 0x00>; > + > + power-domains = <&camcc CAM_CC_TFE_0_GDSC>, > + <&camcc CAM_CC_TFE_1_GDSC>, > + <&camcc CAM_CC_TFE_2_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names = "ife0", > + "ife1", > + "ife2", > + "top"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + camss_csiphy0_in_port: port@0 { > + reg = <0>; > + }; > + > + camss_csiphy1_in_port: port@1 { > + reg = <1>; > + }; > + > + camss_csiphy2_in_port: port@2 { > + reg = <2>; > + }; > + > + camss_csiphy3_in_port: port@3 { > + reg = <3>; > + }; > + > + camss_csiphy4_in_port: port@4 { > + reg = <4>; > + }; > + > + camss_csiphy5_in_port: port@5 { > + reg = <5>; > + }; > + }; > + }; > + > + csiphy0: phy@9523000 { > + compatible = "qcom,kaanapali-csi2-phy"; > + reg = <0x0 0x09523000 0x0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>; > + clock-names = "core", > + "timer", > + "ahb"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + power-domain-names = "top", > + "mmcx", > + "mx"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + csiphy0_in_port: port@0 { > + reg = <0>; > + }; > + > + csiphy0_out_port: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > + csiphy1: phy@9525000 { > + compatible = "qcom,kaanapali-csi2-phy"; > + reg = <0x0 0x09525000 0x0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>; > + clock-names = "core", > + "timer", > + "ahb"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + power-domain-names = "top", > + "mmcx", > + "mx"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + csiphy1_in_port: port@0 { > + reg = <0>; > + }; > + > + csiphy1_out_port: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > + csiphy2: phy@9527000 { > + compatible = "qcom,kaanapali-csi2-phy"; > + reg = <0x0 0x09527000 0x0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>; > + clock-names = "core", > + "timer", > + "ahb"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + power-domain-names = "top", > + "mmcx", > + "mx"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + csiphy2_in_port: port@0 { > + reg = <0>; > + }; > + > + csiphy2_out_port: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > + csiphy3: phy@9529000 { > + compatible = "qcom,kaanapali-csi2-phy"; > + reg = <0x0 0x09529000 0x0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY3_CLK>, > + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>; > + clock-names = "core", > + "timer", > + "ahb"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + power-domain-names = "top", > + "mmcx", > + "mx"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + csiphy3_in_port: port@0 { > + reg = <0>; > + }; > + > + csiphy3_out_port: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > + csiphy4: phy@952b000 { > + compatible = "qcom,kaanapali-csi2-phy"; > + reg = <0x0 0x0952b000 0x0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>; > + clock-names = "core", > + "timer", > + "ahb"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + power-domain-names = "top", > + "mmcx", > + "mx"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + csiphy4_in_port: port@0 { > + reg = <0>; > + }; > + > + csiphy4_out_port: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > + csiphy5: phy@952d000 { > + compatible = "qcom,kaanapali-csi2-phy"; > + reg = <0x0 0x0952d000 0x0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY5_CLK>, > + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>; > + clock-names = "core", > + "timer", > + "ahb"; > + > + interrupts = ; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + power-domain-names = "top", > + "mmcx", > + "mx"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + csiphy5_in_port: port@0 { > + reg = <0>; > + }; > + > + csiphy5_out_port: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > camcc: clock-controller@956d000 { > compatible = "qcom,kaanapali-camcc"; > reg = <0x0 0x0956d000 0x0 0x80000>; > @@ -6548,6 +6927,28 @@ pdp_tx: scp-sram-section@100 { > }; > }; > > + csiphy_mxc_opp_table: opp-table-mxc { > + compatible = "operating-points-v2"; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>, > + <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + }; > + > thermal-zones { > cpullc-0-0-thermal { > thermal-sensors = <&tsens0 0>; > -- Best wishes, Vladimir