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Mon, 9 Jun 2025 10:13:49 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , , , Subject: [PATCH v1 07/12] iommu/arm-smmu-v3: Implement arm_smmu_get_viommu_size and arm_vsmmu_init Date: Mon, 9 Jun 2025 10:13:30 -0700 Message-ID: <55b1d69b2cceb685d4eb728a7a53572a9147993a.1749488870.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E5:EE_|CY5PR12MB6107:EE_ X-MS-Office365-Filtering-Correlation-Id: 42e15f66-4bd9-4513-7ce7-08dda7790bad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hHJDvmYKGBjtkrRLS0B21wg/rJ2gDZx+fUZ1qhG5VY2fPBytgXT+Iibxq8Kd?= =?us-ascii?Q?2MoiGPbZKldiMntAkvZhecCaA8inSLozF9xmeA+VgDQL3LpRIEFhlr0ueK07?= =?us-ascii?Q?BEoqT9CDJGBd4GaIMijL4Xt+xqi7v+RrFwamfS6nu6TW9hzi2+ziSTuEbaRM?= =?us-ascii?Q?7n0zlznwlXs/SRkzs3p9FIZ81jef/MUTV9+NhAM5jinBweQNGt0q6rc22/hp?= =?us-ascii?Q?yAyHwq1YaokjMf7szQ8fVm0rBZfG3Mf/z7KUvAOmnzIbCIfIRzbISwmzDY2T?= =?us-ascii?Q?41VA/sRsQhgx7p58pz9BWMG5Efp9gF8CO+M/2ePc9GXXke+UjwpL1jSrhvMY?= =?us-ascii?Q?gIqGjKlC/4ExaSIn+SJZV5hRBjjUng0SVVsyXwauRa/y/YNQCY+/K3kjBQep?= =?us-ascii?Q?Rgu898AXnvO0oUYqM2ZcUxsA+ckdVrlqtacRWlY+YZY1rE3XkZSkbZ/c9djW?= =?us-ascii?Q?8mCy5kE2maxg6fzswr39mjJHJxYhh+d8o+LsNt8/gKN87t+RzjIz4OT9jWDa?= =?us-ascii?Q?FGCCL4uEYgQGkyqhojXGKgmheuXEzOFg1F35VmGCUTA8F+s4RorwhPT5YO2c?= =?us-ascii?Q?BJTkONHXyV5pRgzXUf0J5XDj8vZudHcXro/UWhxuDXWnr4aMJs7BgR9aAlLT?= =?us-ascii?Q?wN9Peud7hIja//Syt21e1+SfZUp7p83OawEGN2AOARB/fOAflmjvv4fg+Ar4?= =?us-ascii?Q?SAXTCr5AV8zFK8AxL5WV4usJBRBNJXYpAD/W/9pvC0vha1T9OnL9TRQzjRqz?= =?us-ascii?Q?8XfpSQ9nNVf9KD8+Kck7M+iio41rFQOhIB5tLWDjEcysWS/X7wsOXAcTREzE?= =?us-ascii?Q?Gy+q/HFyWbgx2rhfRCRLSrsOE+lpOz4EDYqxawagKLlKoC9vxKfBM5ksMZlW?= =?us-ascii?Q?0xO7QxZ57E9DdEysGrbFA2+GmtxTfMHyi1qHRDOQCxlBi4HAd6BA8wIveIRq?= =?us-ascii?Q?yrkXjM3xVjUTH9aqvYDHZp2cyIjTxCN0rYCSTWyw0S/Biwpmkip00HcJJe4h?= =?us-ascii?Q?2XJDnrwUuqqJJDmz5pQEss302cMt9aub2H75MTUSFh7QUw5FwA59xbmryk/2?= =?us-ascii?Q?22Iwlh7BNVd9KpviyuJJrCJHbs4FXZNL1W+ta+JHsu+6w9+1OweKZ6PtSU5e?= =?us-ascii?Q?/RRLreLEOl0GJGreaEIuox0g/Cz1YEGdMwi+96UnnUoDOEx/w6ijMN6zLZb4?= =?us-ascii?Q?vKAOgapiBu8N9kdogGaijisLnLYwGnfuXIwlvqFPFpAjPWrtVRTAm98yrroB?= =?us-ascii?Q?9y7oWl/+pvVSY4VgeIAUNmLvUBrhqzKYycXH6omD2t10GcHKHpZN0Onc5oLe?= =?us-ascii?Q?jYtOyPx0qs80Ji6gfZcwWGxd973vOjFxjRbqoY8tREo7EeitOCb39JJqXi+e?= =?us-ascii?Q?8MOc42XHar3JKo9zvyJnvTH3yzwwCjosZThMVeNUbPrR9r1Jl1cEUE3E802j?= =?us-ascii?Q?d2LhGV47PKY1OwC5ECBt6qAO+it/uJZVR83b941Tz2zQJ4qDnpWv4SqmsSfK?= =?us-ascii?Q?DaF0iI/0ZuSQkyw1fVbC80oFNp2hASGW4Bpz?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2025 17:14:08.3264 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42e15f66-4bd9-4513-7ce7-08dda7790bad X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6107 Sanitize the inputs and report the size of struct arm_vsmmu on success, in arm_smmu_get_viommu_size(). The core will ensure the viommu_type is set to the core vIOMMU object, and pass in the same dev pointer, so arm_vsmmu_init() won't need to repeat the same sanity tests but to simply init the arm_vsmmu struct. The arm_vsmmu_alloc() will be cleaned up once the transition is done. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 ++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 56 +++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 + 3 files changed, 64 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ea41d790463e..2357459099f4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1034,6 +1034,10 @@ struct arm_vsmmu { #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type); +int arm_smmu_get_viommu_size(enum iommu_viommu_type viommu_type, + struct device *dev, size_t *viommu_size); +int arm_vsmmu_init(struct iommufd_viommu *viommu, + struct iommu_domain *parent_domain); struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, struct iommu_domain *parent, struct iommufd_ctx *ictx, @@ -1044,8 +1048,10 @@ void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master); int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt); #else +#define arm_smmu_get_viommu_size NULL #define arm_smmu_hw_info NULL #define arm_vsmmu_alloc NULL +#define arm_vsmmu_init NULL static inline int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index e4fd8d522af8..482a49f5c10c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -382,6 +382,62 @@ static const struct iommufd_viommu_ops arm_vsmmu_ops = { .cache_invalidate = arm_vsmmu_cache_invalidate, }; +int arm_smmu_get_viommu_size(enum iommu_viommu_type viommu_type, + struct device *dev, size_t *viommu_size) +{ + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_device *smmu = master->smmu; + + if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) + return -EOPNOTSUPP; + + /* + * FORCE_SYNC is not set with FEAT_NESTING. Some study of the exact HW + * defect is needed to determine if arm_vsmmu_cache_invalidate() needs + * any change to remove this. + */ + if (WARN_ON(smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) + return -EOPNOTSUPP; + + /* + * Must support some way to prevent the VM from bypassing the cache + * because VFIO currently does not do any cache maintenance. canwbs + * indicates the device is fully coherent and no cache maintenance is + * ever required, even for PCI No-Snoop. S2FWB means the S1 can't make + * things non-coherent using the memattr, but No-Snoop behavior is not + * effected. + */ + if (!arm_smmu_master_canwbs(master) && + !(smmu->features & ARM_SMMU_FEAT_S2FWB)) + return -EOPNOTSUPP; + + if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return -EOPNOTSUPP; + + *viommu_size = VIOMMU_STRUCT_SIZE(struct arm_vsmmu, core); + return 0; +} + +int arm_vsmmu_init(struct iommufd_viommu *viommu, + struct iommu_domain *parent_domain) +{ + struct arm_vsmmu *vsmmu = container_of(viommu, struct arm_vsmmu, core); + struct arm_smmu_device *smmu = + container_of(viommu->iommu_dev, struct arm_smmu_device, iommu); + struct arm_smmu_domain *s2_parent = to_smmu_domain(parent_domain); + + if (s2_parent->smmu != smmu) + return -EINVAL; + + vsmmu->smmu = smmu; + vsmmu->s2_parent = s2_parent; + /* FIXME Move VMID allocation from the S2 domain allocation to here */ + vsmmu->vmid = s2_parent->s2_cfg.vmid; + + viommu->ops = &arm_vsmmu_ops; + return 0; +} + struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, struct iommu_domain *parent, struct iommufd_ctx *ictx, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 10cc6dc26b7b..eef1fbd68914 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3688,6 +3688,8 @@ static struct iommu_ops arm_smmu_ops = { .get_resv_regions = arm_smmu_get_resv_regions, .page_response = arm_smmu_page_response, .def_domain_type = arm_smmu_def_domain_type, + .get_viommu_size = arm_smmu_get_viommu_size, + .viommu_init = arm_vsmmu_init, .viommu_alloc = arm_vsmmu_alloc, .user_pasid_table = 1, .pgsize_bitmap = -1UL, /* Restricted during device attach */ -- 2.43.0