From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753572AbbCWWKa (ORCPT ); Mon, 23 Mar 2015 18:10:30 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:46471 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753218AbbCWWK1 (ORCPT ); Mon, 23 Mar 2015 18:10:27 -0400 Message-ID: <55c570957f9bac126093c9412e5797e9.squirrel@www.codeaurora.org> In-Reply-To: <550FF006.6090600@codeaurora.org> References: <1426276174-17010-1-git-send-email-sviau@codeaurora.org> <1426276174-17010-4-git-send-email-sviau@codeaurora.org> <550FF006.6090600@codeaurora.org> Date: Mon, 23 Mar 2015 17:10:25 -0500 Subject: Re: [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines From: =?iso-8859-1?Q?=22St=E9phane_Viau=22?= To: "Archit Taneja" Cc: "Stephane Viau" , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com User-Agent: SquirrelMail/1.4.22-4.el6 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7BIT X-Priority: 3 (Normal) Importance: Normal Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Archit, > Hi Stephane, > > On 03/14/2015 01:19 AM, Stephane Viau wrote: >> Some interfaces (WB, DSI Command Mode) need to be kicked off >> through a START Signal. This signal needs to be sent at the right >> time and requests in some cases to keep track of the pipeline >> status (eg: whether pipeline registers are flushed AND output WB >> buffers are ready, in case of WB interface). >> >> Signed-off-by: Stephane Viau >> --- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 + >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 31 ++-- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 >> ++++++++++++++++++++++++---- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 72 +++----- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 13 +- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 + >> 7 files changed, 276 insertions(+), 97 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >> b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >> index c078f30..72c075a 100644 >> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >> @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = { >> .ctl = { >> .count = 5, >> .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, >> + .flush_hw_mask = 0x0003ffff, >> }, >> .pipe_vig = { >> .count = 3, >> @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = { >> .ctl = { >> .count = 5, >> .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, >> + .flush_hw_mask = 0x003fffff, > > msm8x16 would require a flush_hw_mask too, it should be 0x32a59 if I'm > not wrong. Could you please add it for the next revision, or as a part > of the 8x16 hw cfg patch? Correct; thanks for pointing this out. IMO, this value should be 0x4003ffff because the fields are actually present in the register (even though the interfaces/pipes.etc. are not). Anyway, these bits won't be accessed because the driver won't even allow the usage of the corresponding resources. I will update in the v2 of "drm/msm/mdp5: Add hardware configuration for msm8x16". Thanks, Stephane. > > Thanks, > Archit > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" > in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project